Senior/Principle Engineer - Power Semiconductors Definition and Reliability

• Participate in the development of the power device (Si, GaN, DrMOS) reliability platform at headquarters, and propose reliability characterization methods.

• Participate in the roadmap planning for power devices at headquarters. Contribute to specification definition of roadmap power devices.

• Production of insight reports about technological development trends and industry roadmap of power devices (Si, GaN, DrMOS).

• Feasibility analysis of new cutting-edge concepts related to power device development.

• Build and maintain cooperation with industrial institutions and universities in Europe.   

• (Required) Ph.D. in Materials Science and Engineering (or related field) with a minimum of 2 years of R&D experience after graduation, or M.Sc. with several years of advanced R&D experience in world-class corporate or research institutes within semiconductor domain.

• Demonstrated technical portfolio with granted patents, peer-reviewed publications (e.g., IEEE, APEC, PCIM), or widely-adopted open-source projects.

• Proven solid experience on power semiconductor development.

• Proven solid experience on reliability analysis and failure analysis of power semiconductors.

• Expertise on power semiconductor physics and process flows.

• Deep knowledge of dynamic switching processes and parasitic interactions in Si/GaN power stages. Ability to map non-linear devise parasitic and gate charges dynamics to VRM efficiency, ringing stress, and reliability margins.

• Expertise in Double Pulse Testing (DPT), dynamic Rdson testing, and high-frequency, high-bandwidth measurement techniques.

• Knowledge about high-frequency, high current DC-DC converter and VRM applications.

• Participation, representing the local research center, in internal and external events (e.g, conferences, workshops, etc).

• Fluent level of communication in English.

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