7d ago
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CPU–SoC Mask Layout Designer (Diploma Level Contract role) - Silicon Engineering Group (SiG)

2 Locationsmid
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Quick Summary

Key Responsibilities

Creates mask layouts of integrated circuits for a given specification and runs complete set of design verification tools for process design rules, electron migration, voltage drop (IR), ESD,

Requirements Summary

Who We're Looking For:By applying to this posting,

Technical Tools
OtherDesigner

Just completed your diploma in Electrical and Electronic Engineering and ready to take the next step? Start your career with a role that gives you hands-on experience at the heart of semiconductor innovation. At Intel, you'll be immersed in real engineering challenges from day one, developing practical skills and industry knowledge that will accelerate your professional growth.

In this position, you will be involving in the training, design and development of next generation SOC/CPU for wide range of Intel products. Your responsibilities will include some of the following but not limited to:

  • Creates mask layouts of integrated circuits for a given specification and runs complete set of design verification tools for process design rules, electron migration, voltage drop (IR), ESD, and other reliability checks on the layouts.

  • Creates accurate designs that meet project needs, applying understanding of design manuals, established processes, layout elements, and basic electronic principles.

  • Works with multiple internal and external stakeholders to align on projects, provide updates, and resolve issues.

  • Designs and analyses floorplans, power grid, and bumps and performs all required verification on the layout blocks.

  • Troubleshoots a wide variety of issues up to and including layouts and tool/flow/methodology used in layout design.

Requirements

~1 min read

Who We're Looking For:
By applying to this posting, you are expressing interest in Diploma level contract job opportunities with Intel for which your qualifications relevant to the below

  • Diploma in Electrical and Electronic Engineering or related fields

  • Strong technical fundamentals and good communication skills, proficiency in English

  • Curious, motivated, and eager to grow in semiconductor design

  • Familiarity with Unix, VLSI, SoC/CPU Architecture, or System Verilog is a plus

  • Candidates must be open to contract-based position

  • Candidates must be willing to work in Penang location

  • Positions open only to Diploma fresh graduate

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.

*

ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.

Location & Eligibility

Where is the job
—
Location terms not specified
Who can apply
Same as job location

Listing Details

Posted
September 22, 2026
First seen
September 29, 2026
Last seen
September 29, 2026

Posting Health

Days active
0
Repost count
0
Trust Level
32%
Scored at
September 29, 2026

Signal breakdown

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CPU–SoC Mask Layout Designer (Diploma Level Contract role) - Silicon Engineering Group (SiG)