IA Core Post Silicon Validation Engineer

Join Intel's All Cores Engineering (ACE) Group as a Post Silicon Validation Engineer. Our team delivers Intel's industry leading P-Core IP solutions to our Xeon Server products for Data Center and Cloud customers.

Intel Architecture (IA) Core Post Silicon Validation Engineers are responsible for core level validation of the leading CPU products of each new Intel P-Core product. To bring these features and new platforms to market, a Core Post-Si Validation Engineer needs to be an expert in CPU Post-Si debug and validation, have knowledge in test generators for core level validation, be involved in tasks such as developing validation plans, 'powering on' the very first system built with Intel's latest and greatest CPU, validating product features, and identifying and debugging all functional bugs.

Our Engineers have great opportunities to enhance their skills in validation architecture and design. Various validation techniques are used, such as emulation, while offering a unique hardware-software experience.

In addition to various tools, languages and validation methodologies, Engineers will develop expertise with Intel Architecture and Micro Architecture and will be deeply involved in the process of defining new Intel features. They are independent, creative, with the willingness to innovate new solutions and demonstrate uncompromised quality in their work. Good communication and interaction skills among groups is also important.

You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.

Minimum Qualifications

• Bachelor’s degree in electrical/computer engineering or computer science and 6+ years of experience -OR- a master’s degree in electrical/computer engineering or computer science and 4+ years of experience -OR- a PhD in Electrical/Computer Engineering or Computer Science and 2+ years of experience in:
• C++ or Perl or Python
• CPU architecture / assembly
• Debug

Preferred Qualifications

• MCA (Machine Check Architecture)
• RAS (Reliability Availability Serviceability) / SER (Soft Error Rate)
• Emulation
• Chip logical validation concepts and methodologies

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