Memory Electrical Validation Engineer

At Intel, innovation starts with you. We are pushing the limits of silicon, AI, and edge-to-cloud architecture to power breakthrough technologies worldwide. Here, your skills will drive meaningful impact, solving real-world challenges and defining the next era of tech. Join our team and lead the future of engineering.
Join Intel's Memory Validation Team as a Memory Electrical Validation Engineer, where you will serve as a technical expert and lead validator for cutting-edge memory technologies embedded in mobile and desktop CPU products.
In this role, you will be responsible for leading the electrical validation strategy, signal integrity compliance, and system margin analysis for Intel's memory interfaces. You will drive complex post-silicon debug, refine Memory Reference Code (MRC) requirements, and collaborate closely with cross-functional design, architecture, and firmware teams to ensure robust product quality, high-volume production readiness, and optimal silicon performance.

• →Electrical Validation Strategy Execution
  Lead Validation Execution: Define, own, and execute comprehensive electrical validation (EV) test strategies and plans for high-speed memory I/O interfaces to achieve aggressive performance, quality, and production goals.
• →Signal Integrity /System Margin: Validate analog circuit performance, signal integrity compliance (SIV/SMV), and system-level electrical margins across temperature, voltage, and process corners to ensure stable operation.
• →Test Infrastructure / Automation: Design, execute, and continuously optimize validation procedures, specialized test automation frameworks, and system margin analysis tooling.
• →Post-Silicon Debug / Design Collaboration
  Complex Failure Triage: Drive deep-dive debug for electrical design features, identifying root causes for functional, parametric, and triage failures.
• →Lead DOEs: Formulate and execute multi-variable Design of Experiments (DOEs) in close collaboration with circuit design, logic, and pre-silicon teams to drive silicon issues to resolution.
• →I/O Interaction Testing: Characterize complex interactions between electrical design elements, board-level environments, and silicon features using post-silicon validation infrastructure.
• →Firmware Optimization/Cross-Functional Alignment
  MRC Analysis / Tuning: Analyze, refine, and optimize Memory Reference Code (MRC) steps, calibration values, and firmware algorithms for margin, power, and quality improvements.
• →Cross-Team Integration: Collaborate directly with architecture, circuit design, pre-silicon verification, and system integration teams to ensure robust validation coverage across the entire memory subsystem.
• →Technical Guidance: Provide technical direction and mentorship to junior validation engineers on validation methodologies and debug techniques.

• 6+ years of experience in high-speed mixed-signal IP electrical validation, high-speed I/O characterization, or signal integrity (SI/PI) analysis.
• Deep domain experience with modern high-speed memory technologies (e.g., DDR5, LPDDR5/5X, LPDDR6) and JEDEC interface specifications.
• Proven track record of leading complex root-cause debug investigations (DOEs) across multidisciplinary teams (Design, Logic, FW).
• Proficiency with high-speed lab equipment (oscilloscopes, BERTs, logic analyzers) and scripting languages (Python, C/C++) for test automation and data analysis.

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