Physical Design for PPA Optimization Engineer
Quick Summary
Minimum Qualifications BSc or MSc in Electrical Engineering, Computer Engineering, or a related field Hands-on experience in physical or circuit design Basic scripting experience using Python, Tcl,
Our team is dedicated to optimizing Intel’s cutting-edge process technology to meet the rapidly evolving needs of next-generation silicon designs. Operating at the intersection of process and design development, we drive continuous innovation in both physical design and methodology. We partner closely with Core and SoC design teams worldwide to drive both process and product-level optimization - directly enabling Intel to deliver highly competitive, high-performance and low-power products.
Role Overview
As a Physical Design & PPA Optimization Engineer, you will play a key role in achieving best-in-class Power, Performance, and Area (PPA) for Intel IPs. You will be responsible for identifying optimization opportunities, developing physical design optimization methodologies, executing the full physical design flow to evaluate PPA landing zones on new Intel process technologies, and translating findings into actionable recommendations that influence strategic decision-making and product direction.
Key Responsibilities
Define and implement DTCO experiments to evaluate the interaction between process technology and physical design implementation.
Define and develop design optimization methodologies across all physical design flow domains, such as placement, CTS, routing, and timing closure
Run the full PnR flow to evaluate new technology impacts on PPA metrics.
Identify trade-offs and optimization opportunities at the device, cell, and block
Requirements
~1 min read- BSc or MSc in Electrical Engineering, Computer Engineering, or a related field
- Hands-on experience in physical or circuit design
- Basic scripting experience using Python, Tcl, or a similar language
- Strong analytical and problem-solving skills
- Ability to analyze implementation results and communicate conclusions clearly
- 2+ years of experience in physical design or circuit design
- Familiarity with physical design implementation flows and methodologies
- Solid understanding of transistor, cell, and block-level PPA trade-offs
- Experience developing physical design methodologies and analysis tools
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Location & Eligibility
Listing Details
- Posted
- September 23, 2026
- First seen
- September 29, 2026
- Last seen
- September 29, 2026
Posting Health
- Days active
- 0
- Repost count
- 0
- Trust Level
- 33%
- Scored at
- September 29, 2026
Signal breakdown
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