20d ago
New

Semiconductor Packaging Research Engineer

2 Locationsmid
OtherResearch Engineer
1 views0 saves0 applied

Quick Summary

Key Responsibilities

define integration flows, research vehicles, DOE, defect/yield learning,

Requirements Summary

develop and validate thermal, thermo-mechanical, electrical, reliability, or multi-physics models using experimental and failure analysis data. Translate product needs into research hypotheses,

Technical Tools
OtherResearch Engineer

Intel is shaping the future of technology to help create a better future for the entire world. Our work in pushing forward fields like AI, analytics, and cloud-to-edge technology is at the heart of countless innovations. With a career at Intel, you'll have the opportunity to use technology to power major breakthroughs and create enhancements that improve our everyday quality of life. Join us and help make the future more wonderful for everyone. Want to learn more? Visit our YouTube Channel or the link below.

Life at Intel

Responsibilities

~1 min read
  • →

    Research advanced packaging concepts such as chiplets, heterogeneous integration, 2.5D/3DIC, hybrid bonding, interposer, and die-to-die interconnects. 

  • →

    Drive either process integration learning or modeling/simulation to assess feasibility, reliability, manufacturability, and technology readiness. 

  • →

    For process integration: define integration flows, research vehicles, DOE, defect/yield learning, qualification evidence, and risk mitigation paths. 

  • →

    For modeling: develop and validate thermal, thermo-mechanical, electrical, reliability, or multi-physics models using experimental and failure analysis data. 

  • →

    Translate product needs into research hypotheses, technical plans, and recommendations; document outputs through reports, design guidance, IP, publications, and development-transfer inputs. 

  • →

    Collaborate across research, design, process, materials, reliability, manufacturing, supplier, university, and ecosystem teams. 

Requirements

~2 min read

Minimum qualifications are required to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.

  • Master’s or Ph.D. in Mechanical Engineering, Electrical Engineering, Materials Science, Applied Physics, Computational Mechanics, Microelectronics, Semiconductor Manufacturing, or related field. 

  • 1+ years’ experience in semiconductor packaging research, advanced packaging integration, process integration, modeling/simulation, reliability, materials, or heterogeneous integration. 

  • 1+ years' experience in one or more of the following areas: process integration, research vehicle execution, DOE, defect/yield learning, reliability, model development& validation, or multi-physics simulation. 

  • 1+ years' experience with advanced packaging technologies such as flip chip, chiplets, 2.5D/3DIC, fan-out, hybrid bonding, interposers, HBM integration, advanced substrates, or die-to-die interconnects.

​ 

  • Ph.D. or deep technical specialization in packaging process integration, computational mechanics, thermal sciences, electrical modeling, materials reliability, or microelectronics research and 4+ years of relevant experience.  

  • Experience with prototype builds, technology readiness assessment, research-to-development transfer, package-system co-optimization, or chip-package-board co-design. 

  • Modeling tool experience such as ANSYS, Abaqus, COMSOL, HFSS, Cadence, MATLAB, Python, JMP, or equivalent platforms. 

  • Record of patents, publications, conference presentations, technical reports, methodology development, or competitive technology assessments. 

  • Ability to turn ambiguous research problems into clear assumptions, experiments, learning milestones, qualification metrics, and actionable recommendations. 

 

Our total rewards package goes above and beyond just a paycheck. Whether you're looking to build your career, improve your health, or protect your wealth, we offer generous benefits to help you achieve your goals. Go to Intel Benefits | Intel Careers for details of benefits available to you. Intel reserves the right to modify, change or discontinue benefit plans at any time in its sole discretion.

          

  • Advanced packaging research and pathfinding 

  • Process integration or modeling/simulation expertise 

  • Heterogeneous integration, chiplet, and advanced substrate knowledge 

  • DOE, prototype learning, reliability assessment, or model validation 

  • Technology readiness evaluation and cross-functional communication 

​

College Grad

Shift 1 (United States of America)

US, Arizona, Phoenix

US, Oregon, Hillsboro

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.
N/A

What We Offer

~1 min read

We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. Find out more about the benefits of working at Intel.

 

 

Annual Salary Range for jobs which could be performed in the US: $122,440.00-232,190.00 USD

 

 

The range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process.

 

 

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.

*

ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.

Location & Eligibility

Where is the job
—
Location terms not specified
Who can apply
Same as job location

Listing Details

Posted
September 9, 2026
First seen
September 30, 2026
Last seen
September 30, 2026

Posting Health

Days active
0
Repost count
0
Trust Level
21%
Scored at
September 30, 2026

Signal breakdown

freshnesssource trustcontent trustemployer trust
Newsletter

Stay ahead of the market

Get the latest job openings, salary trends, and hiring insights delivered to your inbox every week.

A
B
C
D
Join 12,000+ marketers

No spam. Unsubscribe at any time.

Semiconductor Packaging Research Engineer