Senior ASIC DFT Engineer

Join us to help build the next generation of AI hardware solutions. You will be part of a highly skilled, agile team developing cutting-edge hardware for the AI domain, where we push the boundaries of what silicon can do for emerging AI workloads.

We are building this team from scratch within Intel. With a startup-like culture, we move quickly and give engineers the opportunity to drive significant technical and business impact.
We are intentional, fast adopters of AI as a working tool, and actively use AI throughout our architecture, design, verification, and development workflows.

If you are energized by defining things that have never existed before, value rigorous thinking, and want real scope and short feedback loops, you'll feel right at home here.

This is a senior, hands-on role with broad technical influence.

You will own central DFT aspects in our new family of chips and will define their architecture, planning and implementation. You'll also play a central role at defining and improving the methodologies and workflows we adopt as a team.

• →Define DFT architecture and strategy for complex AI acceleration IPs and subsystems, balancing test coverage, area, timing, and power.
• →Build the DFT implementation - scan, compression, boundary scan (JTAG), MBIST, and test access/control - and drive fault coverage closure to sign-off.
• →Lead ATPG & pattern generation
• →Contribute to the development of DFT methodologies and working flows, helping drive best practices across the team.
• →Champion and advance the team's use of AI tools across the DFT flow, finding where they add real leverage and helping the team adopt them well
• →Collaborate closely with design, verification, physical design, and product/test engineering teams, and support silicon bring-up, debug, and yield/quality analysis.

• B.Sc. in Electrical Engineering, Computer Engineering, or equivalent.
• 6+ years of hands-on DFT experience, with a strong record of driving DFT solutions from architecture through silicon bring-up.
• Deep command of core DFT techniques: scan insertion, compression, ATPG, boundary scan (JTAG), and MBIST.
• Strong intuition for working with AI tools and real interest in using them to advance the DFT flow.
• Demonstrated ownership of complex DFT solutions and the ability to drive technical decisions across cross-functional teams.

• DFT experience on large, high-performance, or AI/ML accelerator designs.
• Hierarchical DFT, low-power test, in-system test, or silicon debug/bring-up experience.
• Strong familiarity with the broader development cycle, including design, verification, and physical design

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