Senior Physical Design Engineer

Join a team developing next-generation CPU cores that power client, server, IoT, and AI platforms. As a Senior Physical Design Engineer (CPU), you will play a key role in delivering high-performance, power-efficient silicon solutions. You will take ownership of blocks within the CPU core design, driving implementation from RTL to GDS and contributing to advanced physical design methodologies.

• →Own physical design and implementation of CPU core blocks or subsystems
• →Execute synthesis, floorplanning, place and route, and design closure
• →Perform static timing analysis (STA), power analysis, and physical verification
• →Drive convergence of timing, power, and area (PPA) metrics
• →Debug and resolve complex design issues across multiple design stages
• →Develop and optimize design flows and automation scripts
• →Collaborate cross-functionally with RTL design, verification, clocking, and full-chip teams
• →Contribute to improving design methodologies and best practices
• →Provide guidance to junior engineers where applicable

• Strong problem-solving and analytical thinking

• Takes ownership and accountability for deliverables
• Collaborates effectively across multidisciplinary teams
• Communicates technical concepts clearly and concisely
• Prioritizes work effectively in a fast-paced environment
• Continuously learns and applies new tools and methodologies

Qualifications

You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.

Note:

For information on Intel’s immigration sponsorship guidelines, please see

Intel U.S. Immigration Sponsorship Information

Minimum Qualifications and Experience:

Bachelors in Computer / Electrical Engineering  or related field with 7+ years of relevant work experience.  Or a Masters in the same field with 4+ years of relevant work experience.

Your experience described above must be in the following:

• Experience with integrated circuit design tools (ex: Synopsys/Cadence), including logic synthesis, place and route, static timing analysis and design closure
• PV convergence (including static timing and power analysis)
• Chip physical design verification including formal equivalence, timing, electrical rules, DRC/LVS, Noise and electro-migration checks.
• Scripting in an interpreted language, minimum TCL in addition to at least one other (e.g. Perl, Python, Ruby)
• Experience with one or more of the following areas: Synthesis of a digital logic block, which was integrated into a large SoC or IP

Preferred Qualifications and Experience:

• Industry experience/exposure with CPU Micro-Architecture

• Physical design best known practices concerning floor-planning, routing techniques, clock distribution
• Static Timing Analysis, Noise analysis, and reliability verification techniques
• RTL to GDS methodologies and formal equivalence
• Synopsys tool suite (Fusion compiler, ICC2, PrimeTime) or Cadence (genus/innovus)

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