Staff EMIB-T Substrate Yield Engineer

Intel's APTM organization is seeking a highly driven Staff Technology Development Substrate Yield Lead to drive supplier yield, defect reduction, technical issue closure, and process-control maturity supporting next-generation EMIB-T substrates across Japan suppliers.  The team will be chartered to lead yield performance for next-generation advanced packaging technologies, including EMIB-T (Embedded Multi-die Interconnect Bridge with TSV), Intel's most advanced platform for heterogeneous integration partnering with substrate suppliers locally at the HVM factories. 

This is a high-visibility, high-accountability role with significant responsibility for enabling successful technology development and manufacturing readiness across both Intel Foundry Services (IFS) and Intel Product Groups (IPG).

The ideal candidate is a self-starter who thrives in ambiguous and fast-paced environments, proactively drives issues to closure, and requires minimal supervision. Success in this role requires strong technical depth, urgency in execution, the ability to influence cross-functional teams and suppliers, and a relentless focus on delivering yield and program milestones. 

• →Own day-to-day yield performance and issue closure for assigned supplier lines, modules, products, or process areas.
• →Lead structured investigations from containment and hypothesis development through experiments, failure analysis, corrective action, and sustainment.
• →Use statistical and spatial analytics to identify signatures by line, tool, material, panel position, geometry, product, and time.
• →Establish clear supplier actions, owners, completion criteria, control limits, and verification plans.
• →Support DFM/DFY, qualification, ramp readiness, change control, and deployment of dashboards or automated analytics.
• →Capture reusable learning and communicate facts, hypotheses, decisions, and residual risks clearly.

• Masters degree with 6+years or PhD with 4+years in Engineering, Materials Science, Physics, Chemistry, Data Science, or a related technical discipline.
• 5+ years of experience in semiconductor manufacturing, advanced packaging, substrate technology, yield engineering, process engineering, or a closely related field.
• Hands-on experience in substrate, advanced packaging, or semiconductor yield engineering, including statistical analysis, defect reduction, process optimization, SPC, DFM/DFY, defect metrology, failure analysis, and HVM execution.
• Strong analytical and problem-solving skills with the ability to make data-driven decisions in complex environments.
• Experience working across multiple organizations and influencing stakeholders to achieve results.
• Demonstrated ability to independently manage complex technical issues, execute with urgency, and drive actions to closure.
• Experience developing or deploying yield monitoring systems, automated analytics, dashboards, image analytics, computer vision, AI/ML-based defect detection, or automated defect classification systems.

• Experience working directly with substrate suppliers and external manufacturing partners.
• Demonstrated program leadership experience, including coordinating cross-functional technical teams and driving execution in high-visibility, high-impact environments.
• Experience with semi-additive processing, build-up films, microvias, copper plating, lithography, lamination, embedded silicon, TSV, 2.5D/3D packaging, or heterogeneous integration.
• Prior experience supporting technology development, qualification, and manufacturing ramp of advanced semiconductor technologies.
• Experience with automated data pipelines, dashboards, image analytics, computer vision, AI/ML defect detection, or automated defect classification.

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