8d ago
New

Staff SOC DFT Engineer

MalaysiaMalaysia·George Townlead
OtherDft Engineer
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Quick Summary

Key Responsibilities

Develop and implement advanced DFT methodologies for complex SoC designs to maximize test coverage and efficiency. Collaborate with design, verification,

Requirements Summary

Minimum Qualifications : Bachelor's degree in Electrical Engineering, Computer Engineering, or a related field. 5+ years of experience in DFT, SoC design, or rel

Technical Tools
OtherDft Engineer

The Role and Impact
Are you ready to make a significant contribution to cutting-edge semiconductor designs? As a DFT Design Engineer, you will play a critical role in shaping the testability, debuggability and reliability of complex SoC (System-on-Chip) designs. You will work closely with cross-functional teams, influencing designs from concept to production, and ensuring our products meet the highest quality standards. In this role, you will develop innovative DFT/DFD methodologies, optimize workflow with AI, and enhance post silicon efficiency. Your work will directly impact Intel's ability to deliver world-class semiconductor solutions that advance technology across industries.

Key Responsibilities :

  • Develop and implement advanced DFT methodologies for complex SoC designs to maximize test coverage and efficiency.
  • Collaborate with design, verification, and manufacturing teams to define and optimize post silicon strategies and requirements.
  • Integrate DFT/DFD features into RTL and ensure verification of design for testability requirements.
  • Collaborate with post-silicon teams to debug and validate DFT features.
  • Stay current with emerging trends, AI adoption and technologies in DFT/DFD to ensure best practices are incorporated into workflows.

Requirements

~1 min read

Minimum Qualifications :

  • Bachelor's degree in Electrical Engineering, Computer Engineering, or a related field.
  • 5+ years of experience in DFT, SoC design, or related semiconductor design areas.
  • Expertise in RTL design using hardware description languages like Verilog, VHDL, or SystemVerilog.
This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.

*

ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.

Location & Eligibility

Where is the job
George Town, Malaysia
On-site at the office
Who can apply
MY

Listing Details

Posted
September 21, 2026
First seen
September 29, 2026
Last seen
September 29, 2026

Posting Health

Days active
0
Repost count
0
Trust Level
33%
Scored at
September 29, 2026

Signal breakdown

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Staff SOC DFT Engineer