Senior Microarchitecture Researcher

IonQ, Inc. [NYSE: IONQ] is the world’s leading quantum platform and merchant supplier - delivering integrated quantum solutions across computing, networking, sensing, and security. IonQ’s newest generation of quantum computers, the IonQ Tempo, is the latest in a line of cutting-edge systems that have been helping customers and partners including Amazon Web Services, and AstraZeneca achieve 20x performance results and accelerate innovation in drug discovery, materials science, financial modeling, logistics, cybersecurity, and defense. In 2025, the company achieved 99.99% two-qubit gate fidelity, setting a world record in quantum computing performance.

Headquartered in College Park, Maryland, IonQ has operations in California, Colorado, Massachusetts, Tennessee, Washington, Italy, South Korea, Sweden, Switzerland, Canada, and the United Kingdom. Our quantum computing services are available through all major cloud providers, while we also meet the needs of networking and sensing customers across land, sea, air, and space. IonQ is making quantum platforms more accessible and impactful than ever before.  

We are looking for a Microarchitecture (uArch) Researcher. As a uArch researcher, you will be part of a cross-functional team whose mission is to lead IonQ on its journey to build the world's best quantum computers to solve the world's most complex problems.

In this role, you will contribute to the physical implementation, design and layout of fault-tolerant architectures in ion trap quantum processors. You will work on implementing, tailoring, simulating and designing large-scale chip architectures that support fault-tolerant quantum computation. Your work will directly contribute to the physical and logical architecture of the quantum chips of the future.

You will take quantum error correction protocols from theory to a physical layout on ion trap processors, and build the simulation tools that tell us how those layouts perform under realistic noise.

The work is deeply collaborative. You will work alongside trap designers, AMO physicists, QEC researchers and colleagues from a broad range of research backgrounds, and share your results through papers and other technical writing.

• →Contribute to the physical implementation of quantum error correction protocols on ion trap processors.
• →Contribute to a library of simulation tools that analyse logical performance under realistic physical noise models.
• →Collaborate with trap designers, AMO physicists, QEC researchers and a broad spectrum of other research backgrounds.
• →Contribute to research papers and other technical writing.

To succeed, you will need four years of research experience in either quantum computing or chip architecture, and a degree in quantum computing, physics, engineering, chemistry or a related field.

You will bring strong expertise in one or more of AMO theory, QEC theory, QCVV theory or classical VLSI theory, and be comfortable applying it to the architecture of real quantum hardware.

• Strong expertise with quantum simulation techniques, including at the physical, gate, circuit and QEC level.
• Experience with classical chip architecture and an interest in quantum chip architecture.
• Experience with quantum error correction, logical operations and decoders.
• The ability to communicate at every level, from the research community to the business to PhD level.

The total compensation package includes base salary, bonus, equity, and a range of benefits available on our career site.