Lead FPGA /CPLD Engineer (Server & Storage-三重)
Quick Summary
At Jabil (NYSE: JBL), we are proud to be a trusted partner for the world's top brands, offering comprehensive engineering, supply chain, and manufacturing solutions.
This role is responsible for leading a CPLD/FPGA Engineering team that designs and builds innovative Server & Storage products with a world-class team. Provide strategic as well as tactical contributions to the conceptual and detailed CPLD/FPGA design across a variety of Server & Storage products, and provide leadership to the design team as well as other cross-functional disciplines. Be considered as an expert in CPLD/FPGA design with a proven track record of success in team leadership and motivation, program management, and overall project ownership. Demonstrate a detailed understanding of the significance of time to market, risk mitigation, contingency plans, and return on investment.
Responsibilities
~1 min read- →Lead a CPLD/FPGA Engineering team for Server & Storage product development.
- →Define CPLD/FPGA design strategy, architecture, and roadmap aligned with product requirements.
- →Work closely with Hardware, BIOS, BMC, and Firmware teams for CPLD/FPGA design, validation, and maintenance.
- →Drive the implementation of new technologies and design concepts in CPLD/FPGA.
- →Establish and enforce RTL coding standards, design review processes, and best practices across the team.
- →Own test plan development, design specifications, and issue tracking for CPLD/FPGA deliverables.
- →Mentor and develop junior and senior engineers within the team.
Requirements
~1 min readTECHNICAL KNOWLEDGE & SKILLS
- 8+ years of working experience in server CPLD/FPGA development.
- Expert-level proficiency in CPLD/FPGA design and Verilog/VHDL coding.
- Strong experience in I2C, SPI, UART, and SGPIO protocols.
- Extensive experience in RTL coding, simulation, and verification.
- Solid knowledge of CPLD/FPGA development practices, including RTL coding standards, Git version control, and test bench development.
- Thorough understanding of server/storage product architecture and development lifecycle.
- Bachelor's or Master's Degree in Electrical Engineering, or equivalent work experience.
- Minimum 8 years of experience in CPLD/FPGA development in the server/storage industry.
- Experience with 1st-tier branding customers on server/storage systems development (i.e., ODM/OEM) and team leadership is highly preferred.
- Proven ability to lead, motivate, and develop engineering teams.
- Strong organizational and prioritization skills.
- Ability to construct and execute plans within given timeframes.
- Strong analytical skills with the ability to identify problems, trends, and develop solutions.
- Decision-making that reflects the goals and philosophy of the organization.
BE AWARE OF FRAUD: When applying for a job at Jabil you will be contacted via correspondence through our official job portal with a jabil.com e-mail address; direct phone call from a member of the Jabil team; or direct e-mail with a jabil.com e-mail address. Jabil does not request payments for interviews or at any other point during the hiring process. Jabil will not ask for your personal identifying information such as a social security number, birth certificate, financial institution, driver’s license number or passport information over the phone or via e-mail. If you believe you are a victim of identity theft, contact your local police department. Any scam job listings should be reported to whatever website it was posted in.
Jabil, including its subsidiaries, is an equal opportunity employer and considers qualified applicants for employment without regard to race, color, religion, national origin, sex, sexual orientation, gender identity, age, disability, genetic information, veteran status, or any other characteristic protected by law.
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Location & Eligibility
Listing Details
- First seen
- September 27, 2026
- Last seen
- September 27, 2026
Posting Health
- Days active
- 0
- Repost count
- 0
- Trust Level
- 56%
- Scored at
- September 27, 2026
Signal breakdown
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