Jrc4d ago

Senior Standard Cell Design Engineer

EngineeringDesign Engineer

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Overview

Who We Are ( video ) At JRC, we tackle some of the toughest challenges faced by the Department of Defense (DoD) and other government agencies.

Technical Tools

EngineeringDesign Engineer

~1 min read

→Execute the design and development of Radiation Hardened LEAP Standard Cell Libraries across multiple advanced foundry technology nodes.
→Generate and validate new standard cells and IP, including combinatorial logic, sequential logic, and power management cells.
→Leverage in-house software and industry-standard SPICE tools to calculate radiation-induced error rates to ensure circuit resilience.
→Execute advanced library characterizations to optimize Power, Performance, and Area (PPA) in harsh environments.
→Collaborate directly with external foundry partners on Multi-Product Wafer (MPW) runs and provide technical design support to customers.
→Contribute to the development of proprietary simulation software and automation scripts to improve reliability prediction.

Master’s degree with 2+ years of direct industry experience, OR a Bachelor’s degree with 4+ years of experience.
Must be eligible to obtain a U.S. security clearance due to the nature of defense-related projects.
Deep knowledge of semiconductor design methodologies and principles.
Hands-on experience with standard cell design, circuit design, and layout, and associated design tools (e.g. Virtuoso, Spectre, HSPICE)
Demonstrated experience being involved in test-chip designs and MPW execution.
Proficiency in design flows including DRC/LVS, timing analysis, and power integrity.
Extensive experience with simulation tools, specifically for library characterization.

~1 min read

Master’s degree with 5+ years of experience, or Bachelor’s with 7+ years in industry.
Hands‑on design experience with GAA nodes (e.g., Intel 18A), including device architecture and design‑rule familiarity.
Proven background in SRAM/NVM bitcell design and/or memory compiler development.
Practical experience with Liberate, PrimeLib, and SiSmart for characterization and modeling.
Expertise in RHBD for SEE/SEU mitigation, plus proficiency in C++ and scripting (Python/TCL) across advanced nodes (FinFET, GAA, SOI).