~48m ago
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Senior Signal & Power Integrity Engineer

4 Locationssenior
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Quick Summary

Key Responsibilities

Design low-speed I/O channels such as clock circuits, DDR/memories and other sensitive signals. Design layout guidelines for our packages and PCBs (for switches, adapters and electro-optical modules).

Requirements Summary

B.Sc. in Electrical Engineering (or equivalent experience) 5+ years of experience Expert with low-speed I/O simulations and design concepts including clock circuits, DDR/memories ,

Technical Tools
Other

We are looking for Senior Signal & Power Integrity Engineer.

NVIDIA has continuously reinvented itself over two decades. Our invention of the GPU in 1999 sparked the growth of the PC gaming market, redefined modern computer graphics, and revolutionized parallel computing. More recently, GPU deep learning ignited modern AI - the next era of computing. NVIDIA is a “learning machine” that constantly evolves by adapting to new opportunities that are hard to solve, that only we can tackle, and that matter to the world. This is our life’s work, to amplify human creativity and intelligence!

We work closely with NVIDIA sites in USA and China and have access to extensive knowledge, technologies and tools. Taking the products from concepting, through design, implementation, verification and release to customers. If you thrive working with highly skilled people that enjoy reaching challenging goals then NVIDIA might be the perfect workplace for you. This is a dynamic team working with state of the art, unique technology.

If you are someone that loves a challenge, come join this diverse team and help move the needle !

Responsibilities

~1 min read
  • →Design low-speed I/O channels such as clock circuits, DDR/memories and other sensitive signals.  
  • →Design layout guidelines for our packages and PCBs (for switches, adapters and electro-optical modules).
  • →Design package/board/system SI/PI design activities, including PCB stack-up/material selection, design guide implementation, layout review and post-layout analysis.
  • →Work closely with Architecture, ASIC, Mixed Signal, Package, and PCB design teams to design and ensure system SI/PI performance meets expectation.
  • →Simulate passive and active elements in 3D and 2D simulation tools.
  • →Measure systems in the lab using Network Analyzer, TDR and scope.
  • →Work in an intense environment and control multi-discipline expertise

Requirements

~1 min read
  • B.Sc. in Electrical Engineering (or equivalent experience)
  • 5+ years of experience
  • Expert with low-speed I/O simulations and design concepts including clock circuits, DDR/memories , transmitter & receiver design and equalization schemes.
  • Expert level proficiency with time domain analysis and tools.
  • Excellent understanding in electromagnetic waves including transmission line theory and via properties.
  • High level proficiency with electromagnetic tools (such as Ansys EM, CST, etc.)
  • Experience in Lab measurements including VNA & TDR.
  • Ability to work in an intense environment and control multi-discipline expertise.
  • M.Sc./Ph.D. in Electrical Engineering.
  • Expert with time domain co-simulation of I/O circuits and PDN models.
  • Familiar with NRZ/PAM-4 signaling schemes.
  • Experience with MATLAB, Python, and C.

With competitive salaries and a generous benefits package, we are widely considered to be one of the technology world’s most desirable employers.

We have some of the most forward-thinking and hardworking people in the world working for us and, due to unprecedented growth, our exclusive engineering teams are rapidly growing.

If you're a creative and autonomous engineer with a real passion for technology, we want to hear from you.

Location & Eligibility

Where is the job
Not specified
Location terms not specified
Who can apply
Same as job location

About this job

Posted
Today
Employer
has 1,407 open jobs on Jobera.

Listing Details

First seen
October 18, 2026
Last seen
October 18, 2026

Posting Health

Days active
0
Repost count
0
Trust Level
49%
Scored at
October 18, 2026

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Senior Signal & Power Integrity Engineer