~7m ago
New

Silicon Co-design Intern - 2027

ChinaChina·Shanghaientry
Other
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Quick Summary

Key Responsibilities

Work proactively on GPU/SOC feature/IP bring-up and characterization including creating validation, tuning and optimization methodologies, develop proper test plan and test cases.

Requirements Summary

Pursuing BS or MS degree in Microelectronics/Electronic Engineering/Computer and Related Professionals. EE fundamentals, knowledgeable in digital design, computer architecture, power analysis,

Technical Tools
Other

NVIDIA's GPUs and SOCs are the world leaders in performance and efficiency, and we are continually innovating in creative and unique ways to improve our ability to deliver extraordinary solutions in a wide range of sectors. We are seeking engineers who are passionate about what they do and are committed to making a difference in the world through their inventions.

The Silicon Co-Design Group is where architecture intent becomes silicon reality. We own the boundary between what was designed and what was built, and we are the team that knows the difference. When a program ships at frequency and at quality, this team is a reason why.

Responsibilities

~1 min read
  • →

    Work proactively on GPU/SOC feature/IP bring-up and characterization including creating validation, tuning and optimization methodologies, develop proper test plan and test cases.

  • →

    Perform system level use case analysis/profiling and feature return-on-investment investigations, prototype and validation, design methods and control policies to bring the new technology into production and transcend product goals.

  • →

    Collaborate across System Architecture, DFT, ASIC, SW/FW, platform, validation, and production teams throughout the product life cycle on system-level architecture, design, productization, debugging, and deployment for complex silicon designs to improve quality, safety, and manufacturability.

  • →

    Design tools/script to automate product definitions, data collection, test case execution, and results analysis. Provide detailed data analysis of functionality, performance, and latency.

  • →

    Hands on actions on silicon bring-up, validation, and debug; Coordinate product level feature deployment to achieve high product quality at aggressive schedule.

Requirements

~1 min read
  • Pursuing BS or MS degree in Microelectronics/Electronic Engineering/Computer and Related Professionals. 

  • EE fundamentals, knowledgeable in digital design, computer architecture, power analysis, timing analysis, fault analysis, sampling, statistics, and scripting.

  • Experience in one or more areas of high-performance circuit (Low power, PLLs and clocking, SerDes and high-speed IO, SRAMs, power delivery/regulation, security circuits etc).

  • Good understanding of firmware/driver structures and their interaction with HW is a plus.

  • Experience with Python script development, Windows and Linux OS is a plus.

  • Hands-on lab experience with silicon bring up, frequency and power characterization, Tester to System correlation, lab tools (oscilloscopes, multimeters, DAQ). 

  • Excellent problem solving, collaborative, and interpersonal skills. 

  • Excellent verbal communication and written, presentation skills in both Chinese and English.

  • Effective in a collaborative environment.

With competitive salaries and a generous benefits package, NVIDIA is widely considered to be one of the technology world’s most desirable employers. We welcome you join our team with some of the most hard-working people in the world working together to promote rapid growth. Are you passionate about becoming a part of a best-in-class team supporting the latest in GPU and AI technology? If so, we want to hear from you. 

Location & Eligibility

Where is the job
Shanghai, China
On-site at the office
Who can apply
CN

About this job

Who can apply
China
Posted
Today
Employer
has 2,008 open jobs on Jobera.

Listing Details

First seen
October 18, 2026
Last seen
October 18, 2026

Posting Health

Days active
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Trust Level
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Scored at
October 18, 2026

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Silicon Co-design Intern - 2027