Senior Analog IC Layout Engineer
Seoul (jung-Gu)senior
Other
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Quick Summary
Requirements Summary
Bachelor or Master Degree in Electrical Engineering, Electronics,
Technical Tools
Other
About the Team
NXP Semiconductors is seeking an experienced Analog IC Layout Engineer to join the Central Layout Group serving the Power & Energy Business Line, with a primary focus on Automotive Power Solutions (APS).
The Central Layout Group delivers physical implementation expertise for complex mixed-signal and power management integrated circuits supporting multiple product lines worldwide. The team collaborates with Design, Verification, Package, Test and Product Engineering organizations across a global R&D network to drive the successful execution of advanced automotive and industrial semiconductor products.
Role Summary
The successful candidate will play a key role in the development of complex automotive mixed-signal and power management ICs, driving layout execution from planning through tape-out while collaborating with stakeholders across multiple worldwide engineering sites.
Responsibilities：
Layout Execution
- Lead the physical implementation of Analog and Mixed-Signal integrated circuits
- Define and optimize floorplans for complex blocks and top-level assemblies
- Drive layout activities from planning through tape-out
- Ensure design quality, robustness and compliance with development methodologies
Verification and Sign-Off
- Own DRC, LVS, ERC and physical sign-off activities
- Support extraction analysis and post-layout verification
- Drive root-cause analysis and resolution of layout-related challenges
Technical Leadership
- Coordinate layout activities with Design, Verification, Package, Test and Product Engineering teams
- Mentor junior engineers and share technical expertise
- Contribute to layout methodology improvements and best practices
- Support project execution through accurate planning, communication and risk management
Requirements:
- Bachelor or Master Degree in Electrical Engineering, Electronics, Physics or Microelectronics
- Strong experience in Analog IC Layout development
- Expertise with Cadence Virtuoso Layout environment
- Experience with DRC/LVS sign-off methodologies
- Solid understanding of CMOS, BCD, SOI and Mixed-Signal design environments
- Ability to work independently and manage complex technical challenges
- Strong communication, collaboration and stakeholder management skills
- Fluent written and spoken English
Preferred Qualifications
- Experience with Calibre, PVS, Quantus, StarRC or equivalent EDA tools
- Experience with automotive semiconductor products
- Knowledge of High Voltage technologies
- Experience in layout automation and scripting (SKILL, Python, TCL or Shell)
- Previous mentoring or technical leadership experience
- Experience working in multi-site international R&D organizations
- Interest in AI-assisted engineering and design productivity solutions
Location & Eligibility
Where is the job
Seoul (jung-Gu)
On-site at the office
Who can apply
Same as job location
About this job
- Posted
- Today
Listing Details
- First seen
- October 18, 2026
- Last seen
- October 18, 2026
Posting Health
- Days active
- 0
- Repost count
- 0
- Trust Level
- 51%
- Scored at
- October 18, 2026
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