Senior Lead Engineer - IP Design

• →Self starter with 8 to 12 years of experience to Architect and Design complex IP design / Sub-system with minimal supervision.
• →Experience in High Speed Serial protocols and associated high speed challenges on controller and PHY for PCIe, Ethernet & Serdes
• →Understanding of key External Memory interface protocols including DDR4 / LPDDR4, QuadSPI Flash interfaces.
• →Experience in microcontroller architecture, bus protocols like AHB/AMBA,AXI.
• →Extensive hands on knowledge of HDLs (Verilog/VHDL), Scripting languages (Perl, Tcl), C/C++ for hardware modeling.
• →Understanding of end to end IP development flow including complex CDC, RDC constructs, IP Synthesis, DFT ATPG coverage.
• →Have worked on Testbench and Testplan development closely with the verification team.
• →Hands on work on pre silicon validation using FPGA/Emulation Board would be a significant added advantage.

• Proficient skills in both written and verbal communication. Can articulate well. 
• Has a sense of Ownership and engages everyone with Trust and Respect. 
• Should demonstrate Emotional Intelligence and Leadership values with ability to work well as a part of team both local and remote or multisite.

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