qualcomm
qualcomm2d ago
New
USD 167100-250700/yr

CPU Server Physical Design Timing Engineer

mid
OtherPhysical Design Engineer
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Quick Summary

Key Responsibilities

* STA setup, convergence, reviews and signoff for multi-mode, multi-voltage domain designs of Oryon CPU Cores. * Timing analysis, validation and debug across multiple PVT conditions using PT/Tempus.

Requirements Summary

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field and 4+ years of Hardware Engineering, Software Engineering, Electrical Engineering,

Technical Tools
OtherPhysical Design Engineer
## Company: Qualcomm Technologies, Inc. ## Job Area: Engineering Group, Engineering Group > CPU Engineering General Summary: NUVIA is now part of Qualcomm. Our mission is to reimagine silicon and create computing platforms that will transform the industry. You will have the opportunity to work with some of the most talented and passionate engineers in the world to create designs that push the envelope on performance, energy efficiency and scalability. About The Role: In this role you will have the opportunity to define, develop and drive CPU timing closure for Oryon CPU Cores. As a CPU Physical Design Timing Engineer, you will work with microarchitecture and RTL design team to develop timing constraints, drive implementation of the designs to meet aggressive power, area and performance goals using industry standard tools/flows. One of your primary responsibilities will lie in coding scripts used with STA native tools and also useful in enabling CPU timing infrastructure and methodology impacting multiple CPU projects in Qualcomm. You will have the opportunity to collaborate with Qualcomm central timing technology & methodology team and also interact with CPU implementation team to drive PPA goals of CPU. You will have the opportunity to carve out a strong professional growth path working on industry leading technology nodes N2/N3. Key Responsibilities: * STA setup, convergence, reviews and signoff for multi-mode, multi-voltage domain designs of Oryon CPU Cores. * Timing analysis, validation and debug across multiple PVT conditions using PT/Tempus. * Run Primetime and/or Tempus for STA flow optimization and Spice to STA correlation. * Find out the root cause of timing miscorrelation at different design levels in functional and test mode, propose solutions. * Evaluate multiple timing methodologies/tools on different designs and technology nodes. * Work on automation scripts within STA/PD tools for methodology development. * Good Technical writing and Communication skills, should be willing to work in cross-collaborative environment * Strong experience in design automation using TCL/Perl/Python. * Familiar with digital flow design implementation RTL to GDS : ICC, Innovous , PT/Tempus Minimum Qualifications: • Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field and 4+ years of Hardware Engineering, Software Engineering, Electrical Engineering, Systems Engineering, or related work experience. OR Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field and 3+ years of Hardware Engineering, Software Engineering, Electrical Engineering, Systems Engineering, or related work experience. OR PhD in Electrical Engineering, Computer Engineering, Computer Science, or related field and 2+ years of Hardware Engineering, Software Engineering, Electrical Engineering, Systems Engineering, or related work experience. Preferred Qualification/Skills * Strong expertise in STA timing analysis basics, AOCV/POCV concepts, CTS, defining and managing timing constraints, Latch transparency handling, 0-cycle, multi-cycle path handling * Hands-on experience with STA tools - Prime-time, Tempus * Have experience in driving timing convergence at Chip-level and Hard-Macro level * In-depth knowledge cross-talk noise, Signal Integrity, Layout Parasitic Extraction, feed through handling, * Knowledge of ASIC back-end design flows and methods and tools (ICC2, Innovus) * Expert in scripting languages – TCL, Perl, Python * Basic knowledge of device physics Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries). To all Staffing and Recruiting Agencies: Our Careers Site is only for individuals seeking a job at Qualcomm. Staffing and recruiting agencies and individuals being represented by an agency are not authorized to use this site or to submit profiles, applications or resumes, and any such submissions will be considered unsolicited. Qualcomm does not accept unsolicited resumes or applications from agencies. Please do not forward resumes to our jobs alias, Qualcomm employees or any other company location. Qualcomm is not responsible for any fees related to unsolicited resumes/applications. EEO Employer: Qualcomm is an equal opportunity employer; all qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or any other protected classification. Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law. Pay range and Other Compensation & Benefits: $167,100.00 - $250,700.00 The above pay scale reflects the broad, minimum to maximum, pay scale for this job code for the location for which it has been posted. Even more importantly, please note that salary is only one component of total compensation at Qualcomm. We also offer a competitive annual discretionary bonus program and opportunity for annual RSU grants (employees on sales-incentive plans are not eligible for our annual bonus). In addition, our highly competitive benefits package is designed to support your success at work, at home, and at play. Your recruiter will be happy to discuss all that Qualcomm has to offer – and you can review more details about our US benefits at this link. If you would like more information about this role, please contact Qualcomm Careers.

Location & Eligibility

Where is the job
Location terms not specified

Listing Details

Posted
August 7, 2026
First seen
August 9, 2026
Last seen
August 9, 2026

Posting Health

Days active
0
Repost count
0
Trust Level
51%
Scored at
August 9, 2026

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qualcommCPU Server Physical Design Timing EngineerUSD 167100-250700