Staff Engineer, Digital ASIC Design — Storage Controllers

At SK Hynix Memory Solutions, we're at the forefront of semiconductor innovation, developing advanced memory solutions that power everything from smartphones to data centers. As a global leader in DRAM and NAND flash technologies, we drive the evolution of advancing mobile technology, empowering cloud computing, and pioneering future technologies. Our cutting-edge memory technologies are essential in today's most advanced electronic devices and IT infrastructure, enabling enhanced performance and user experiences across the digital landscape.

We're looking for innovative minds to join our mission of shaping the future of technology. At SK Hynix Memory, you'll be part of a team that's pioneering breakthrough memory solutions while maintaining a strong commitment to sustainability. We're not just adapting to technological change – we're driving it, with significant investments in artificial intelligence, machine learning, and eco-friendly solutions and operational practices. As we continue to expand our market presence and push the boundaries of what's possible in semiconductor technology, we invite you to be part of our journey to creating the next generation of memory solutions that will define the future of computing.

Join our digital ASIC design team to develop IP for next-generation SSD controllers and storage solutions. This role offers opportunities across the controller architecture, including host interfaces, on-chip interconnects, and back-end NAND subsystems. You will translate product requirements into microarchitecture specifications, implement high-quality RTL, and collaborate with verification and physical design teams to deliver production-ready silicon.

You will help shape the performance, power efficiency, and scalability of future storage products, with potential opportunities to explore computational storage, storage for AI workloads, next generation SSD architectures as our technology and product roadmap evolve.

• →Own digital ASIC blocks from requirements and microarchitecture definition through RTL implementation, verification support, and silicon delivery.
• →Develop clear microarchitecture specifications documenting interfaces, data flows, design tradeoffs, and implementation details.
• →Write synthesizable Verilog or SystemVerilog RTL that meets functional, performance, power, and area requirements.
• →Run and resolve findings from RTL lint, clock domain crossing (CDC), and synthesis tools to improve design quality.
• →Collaborate with design verification engineers to develop verification plans, debug simulations using tools such as Synopsys VCS, and resolve functional issues.
• →Work with physical design and timing teams on timing constraints, critical-path optimization, and timing closure.
• →Lead design reviews, provide technical guidance to other engineers, and coordinate with cross-functional teams to meet project milestones.

• Master’s degree in Electrical Engineering, Computer Engineering, or a closely related field.
• Demonstrated experience independently owning complex digital ASIC blocks, with technical depth and judgment appropriate for a Staff Engineer.
• Strong proficiency in synthesizable Verilog or SystemVerilog and synchronous digital design fundamentals.
• Working knowledge of ASIC development flows, including simulation using VCS or an equivalent tool, lint, CDC analysis, logic synthesis, and static timing analysis and timing closure.
• Ability to write clear microarchitecture specifications, debug complex design issues, and communicate effectively across design, verification, and physical design teams.

• Experience designing PCIe or NVMe controller logic.
• Experience with SSD controller architectures, NAND interfaces, or flash storage systems.
• Familiarity with AXI protocols, on-chip interconnects, and high-throughput data movement.
• Experience with CPU subsystems or UCIe interfaces.
• Experience delivering ASIC designs through tapeout and supporting silicon bring-up, validation, or production debug.