Staff DV Engineer
Quick Summary
Ready to make connectivity from space universally accessible, secure and actionable? Then you’ve come to the right place! E-Space is bridging Earth and space to enable hyper-scaled deployments of Internet of Things (IoT) solutions and services.
· Strong proficiency in Verilog and SystemVerilog
· Experience writing tests within an existing UVM verification environment
· Solid understanding of UVM architecture and methodology
· Ability to write C/C++ code for verification purposes
· Some scripting experience in Perl or Python
· Ability to contribute to and help write test plans
· Experience writing and maintaining verification tests
· Ability to debug RTL simulations independently
· Experience leading design verification efforts at the block level
· Experience driving code coverage closure on assigned blocks
6+ years of design verification experience in the semiconductor industry
Location & Eligibility
About this job
- Pay per year
- $120,000–$220,000 a year
- 150% above the $68,076 median for Other jobs on Jobera (138,142 salaries).
- Who can apply
- United States
- Posted
- 186 days ago
Listing Details
- Posted
- May 5, 2026
- First seen
- May 6, 2026
- Last seen
- November 8, 2026
Posting Health
- Days active
- 185
- Repost count
- 0
- Trust Level
- 42%
- Scored at
- November 8, 2026
Signal breakdown
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