Senior Digital PD Engineer

The Advanced Circuits and Power Solutions business is known for delivering industry-leading custom IC system solutions, including display and touch power products, charger power products, camera PMICs, power path devices, sensing devices, and high-performance communication interface products. Our products integrate precision signal chains and highly efficient power components into ultra-small form factors, enabling TI’s best-in-class customers to translate their ideas into high-value products that revolutionize the personal electronics market.

In this team, you will work with and learn from incredibly talented technical leaders who have influenced TI’s technology, productivity, and way of working in creative and impactful ways. You will directly interact with one of TI’s most valued, high-volume customers through intense technical reviews and architecture discussions!

By enabling designs that are highly impactful to TI revenue and working with a critical customer on a versatile set of products, you will find yourself on an accelerated career path.

If you are looking to join an ingenious, vigorous & ambitious team that consistently delivers groundbreaking technologies into the custom mobile electronics world, here is an opportunity for you!

• Technology Roadmap & Vision: Own the strategic direction of physical design at TI, establishing the methodologies, quality benchmarks, and technical judgments that form the foundation for TI's next generation of products.
• Industry & Customer Influence: Serve as TI's technical authority in high-stakes customer engagements and partner discussions, communicating complex physical design decisions with authority and clarity.
• Design Governance & Quality Authority: Act as the global quality authority for the digital backend, owning the sign-off for the complete flow from RTL to GDSII and setting the quality standards that projects across TI measure themselves against.
• Cross-Functional Orchestration: Orchestrate deep collaboration with EDA, Library, Memory, and IP teams to eliminate flow bottlenecks, align execution priorities, and raise the implementation bar across all TI projects.

• Upstream Design Shaping: Embed "design-for-implementation" thinking into early-stage architecture and front-end decisions to mitigate costly backend constraints before they arise.
• Methodology & Flow Engineering: Define and establish TI-wide physical design methodologies and flows, ensuring they are robust, scalable, and optimized for the latest process nodes.
• EDA & Node Qualification: Evaluate and qualify new EDA tools and process nodes, driving adoption decisions through data-driven recommendations and rigorous benchmarking.
• Mentorship: Elevate the physical design community at TI by mentoring engineers, standardizing implementation practices, and building lasting institutional knowledge.

• End-to-End Flow Ownership: Independently drive the entire Physical Design lifecycle, including floorplanning, placement, CTS, routing, and full-chip implementation.
• Timing & Reliability Closure: Lead rigorous Static Timing Analysis (STA) and ensure total closure for EM (Electromigration), IR drop, and Physical Verification (DRC/LVS).
• PPA Optimization: Drive aggressive techniques to optimize Power, Performance, and Area (PPA) to ensure TI’s silicon remains industry-leading and highly competitive.
• Clock & Reset Integrity: Analyze and influence clock, reset, and DFT architectures to ensure they are fully optimized for physical implementation and reliability.

What do we expect from you? (Minimum Qualifications)

• 12+ years of hands-on experience in Physical Design / Digital Backend implementation
• Bachelor's or Master's degree in Electronics Engineering, Electrical Engineering, or VLSI Design
• Proven expertise in RTL-to-GDSII flows using industry-standard EDA tools (Synopsys and/or Cadence toolchain)
• Demonstrated ability to own and deliver complex designs independently from specification through signoff
• Deep knowledge of timing closure, power integrity, signal integrity, and physical verification (DRC/LVS/ERC)
• Strong understanding of process node design rules and implementation constraints
• Experience working with or alongside Library, Memory, and IP teams in a product development context
• Strong written and verbal communication skills, with experience presenting technical content to internal stakeholders or external customers

Preferred Skills/ Experience

• 12–18 years of progressive experience in physical design with increasing ownership and scope
• Hands-on experience with mixed-signal designs — including analog-digital co-design, guard-ring strategies, substrate coupling mitigation, and mixed-signal floor planning
• Prior experience in a Subject Matter Expert, methodology lead, or technical architect capacity — having defined implementation standards that others adopted and built upon
• Familiarity with in-house or customized EDA flow development and scripting (Tcl, Python, Perl)
• Experience with customer-facing roles — design reviews, technology presentations, or pre-silicon collaboration with external customers
• Knowledge of DFT integration within the physical design flow (scan insertion, BIST, boundary scan)
• Exposure to power management architectures and low-power implementation techniques (multi-Vt, power gating, voltage islands)