(Sr. Engineer / Engineer) HSIF Analog Engineer
2 Locationssenior
OtherEngineer
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Quick Summary
Key Responsibilities
This requisition is for an entry-level High-Speed Interface (SerDes) Engineer to strengthen our in-house capability for high-speed PHY/IP development.
Requirements Summary
Experience: 5 year analog design engineer Education: B.S. or M.S. in Electrical Engineering, Computer Engineering, or related field (or equivalent practical experience).
Technical Tools
OtherEngineer
Responsibilities:
This requisition is for an entry-level High-Speed Interface (SerDes) Engineer to strengthen our in-house capability for high-speed PHY/IP development. The candidate will contribute to ongoing product programs and next-generation feasibility studies by executing simulation, verification, and lab characterization tasks under guidance of senior engineers. The role provides a structured growth path toward owning design blocks and driving technical decisions in future tape-outs.
- Execute circuit/system simulations and basic analyses for assigned SerDes related blocks; summarize results and next actions.
- Support block integration and verification activities (interfaces, regressions, corner coverage) in collaboration with analog/digital/layout teams.
- Assist with silicon bring-up and lab characterization by preparing setups, collecting data, and supporting debug and simulation-to-measurement correlation.
- Maintain clear documentation (assumptions, checklists, reports) and contribute to technical reviews with concise updates.
Requirements:
- Experience: 5 year analog design engineer
- Education: B.S. or M.S. in Electrical Engineering, Computer Engineering, or related field (or equivalent practical experience).
- Fundamental knowledge: Solid understanding of circuits and/or digital design fundamentals (devices, amplifiers, feedback, sampling, timing, basic signal integrity concepts).
- Analytical skills: Ability to interpret simulation/measurement results, identify discrepancies, and communicate observations clearly.
- Tools & workflow: Comfortable working in a Linux/UNIX environment; ability to manage simulations, data, and documentation in a structured way.
- Communication & teamwork: Ability to collaborate with cross-functional teams and to document work (reports, slides, checklists) with attention to detail.
- Ownership mindset: Willingness to take on defined tasks, drive them to closure, and ask for help early when blocked.
- Language skills: Business level Japanese and English communication skill
- Mixed-signal simulation: Exposure to SPICE-based simulation (e.g., Spectre/HSPICE) and/or mixed-signal environments (Verilog-AMS/Verilog-A) * Preferred
Location & Eligibility
Where is the job
Not specified
Location terms not specified
Who can apply
Same as job location
About this job
- Posted
- 277 days ago
Listing Details
- Posted
- February 4, 2026
- First seen
- September 26, 2026
- Last seen
- November 8, 2026
Posting Health
- Days active
- 43
- Repost count
- 0
- Trust Level
- 19%
- Scored at
- November 8, 2026
Signal breakdown
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External application
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