Full-Chip STA Signoff Engineer

Key Responsibilities

• Own and execute full-chip Static Timing Analysis (STA) signoff for complex SoC designs.
• Perform timing analysis across multiple modes and corners (MMMC) and ensure complete timing coverage.
• Analyze setup, hold, recovery, removal, minimum pulse width, clock gating, and other timing checks.
• Develop, review, and maintain timing constraints including SDC, clocks, generated clocks, input/output delays, false paths, multicycle paths, and clock uncertainty.
• Debug and resolve timing violations across functional and test modes.
• Perform detailed analysis of critical timing paths, identify root causes, and work with implementation teams on timing closure.
• Review timing reports and distinguish between real violations, constraint issues, and tool-related exceptions.
• Support timing closure through synthesis, place-and-route, ECO, and final signoff stages.
• Validate timing constraints and ensure consistency between RTL, synthesis, STA, and physical implementation environments.
• Analyze clock skew, latency, reconvergence, clock interactions, and clock-domain timing relationships.
• Work with physical design teams to resolve congestion, buffering, routing, transition, capacitance, and timing-related issues.
• Participate in timing signoff reviews and provide actionable recommendations for improving PPA and timing.
• Perform timing correlation between different implementation and signoff stages.
• Automate STA analysis, report generation, and debugging workflows using Tcl, Python, or Perl.
• Ensure timing signoff quality and completeness before tapeout.

Must-Have Skills

• Strong hands-on expertise in STA Signoff.
• 6–17 years of experience in ASIC/SoC physical design or timing analysis.
• Proven experience with full-chip timing signoff for complex designs.
• Strong understanding of Static Timing Analysis concepts and methodologies.
• Excellent knowledge of MMMC timing analysis and timing closure.
• Strong expertise in SDC constraints and timing exceptions.
• Experience analyzing setup/hold violations, clock skew, uncertainty, latency, and critical paths.
• Hands-on experience with industry-standard STA tools such as Synopsys PrimeTime.
• Strong understanding of clock definitions, generated clocks, asynchronous clocks, false paths, and multicycle paths.
• Good understanding of ASIC implementation, synthesis, place-and-route, CTS, ECOs, and physical effects on timing.
• Strong scripting skills in Tcl and/or Python.
• Experience working with large, hierarchical, multi-million-instance SoC designs.

Good-to-Have Skills

• Experience with advanced process nodes and complex SoC designs.
• Knowledge of MCMM/OCV, AOCV, POCV, CPPR, and variation-aware timing analysis.
• Understanding of SI/crosstalk-aware timing analysis.
• Experience with low-power designs, UPF, and multi-voltage timing analysis.
• Exposure to timing ECO implementation and signoff automation.
• Familiarity with formal equivalence checking and physical verification flows.
• Strong debugging, analytical, and problem-solving abilities.

Education

Bachelor's or Master's degree in Electrical Engineering, Electronics, VLSI, Microelectronics, or a related field.