11d ago

Senior DFT Engineer

Other

1 views0 saves0 applied

Quick Summary

Key Responsibilities

Design and roll out advanced test methodologies on NVIDIA’s next-generation silicon platforms. Own and work with cross-functional teams to implement the latest in test access mechanisms, IO BIST,

Requirements Summary

BSEE (or equivalent experience) with 5+ years, MSEE with 3+ years, or PhD in DFT or related domains. Demonstrated knowledge and expertise in defining scan test plans,

Technical Tools

Other

At NVIDIA, our Senior DFT Engineers lead the way in silicon test innovation, ensuring flawless execution and outstanding quality in our next-generation silicon platforms. This is an outstanding opportunity to join a world-class team and make a significant impact in the semiconductor industry!

Responsibilities

~1 min read

→
Design and roll out advanced test methodologies on NVIDIA’s next-generation silicon platforms.
→
Own and work with cross-functional teams to implement the latest in test access mechanisms, IO BIST, memory BIST, and scan compression.
→
Collaborate closely with VLSI and Product Engineering groups to design innovative DFT approaches that advance silicon test technology.
→
Lead end-to-end planning and timely execution of NVIDIA's new chip bring-up efforts, from pre-silicon through production deployment.
→
Develop and standardize methodologies, processes, and workflows for silicon bring-up, crafting reusable checklists and playbooks.
→
Improve cross-team communication, work, and handoffs.
→
Guide and mentor junior engineers, helping them navigate complex build trade-offs to achieve world-class quality and efficiency.

Requirements

~1 min read

BSEE (or equivalent experience) with 5+ years, MSEE with 3+ years, or PhD in DFT or related domains.
Demonstrated knowledge and expertise in defining scan test plans, BIST including memories and IOs, fault modeling, ATPG, and fault simulation.
Excellent analytical skills in verification and validation of test patterns and logic on complex and multi-million gate builds using vendor tools.
Experience in silicon debug and bring-up with an understanding of pattern formats, failure processing, and test program development.
Strong programming and scripting skills.
Excellent written and oral communication skills with the curiosity to work on rare challenges.

Deep understanding of DFT architecture.
Direct bring-up experience on GPU/SoC. Hands-on validation skills with oscilloscopes, logic analyzers, and lab debugging.
Understanding of fault models, DPPM, quality metrics, RAS is a plus.
Knowledge of InSystem Test methodologies, PVT dependencies and VF characterization.
Established proficiency in operating within collaborative, multi-functional environments.

Your base salary will be determined based on your location, experience, and the pay of employees in similar positions. The base salary range is 136,000 USD - 218,500 USD for Level 3, and 168,000 USD - 264,500 USD for Level 4.

You will also be eligible for equity and benefits.

Applications for this job will be accepted at least until October 20, 2026.

This posting is for an existing vacancy.

NVIDIA uses AI tools in its recruiting processes.

NVIDIA is committed to fostering an inclusive work environment and proud to be an equal opportunity employer. As we highly value diversity in our current and future employees, we do not discriminate (including in our hiring and promotion practices) on the basis of race, religion, color, national origin, gender, gender expression, sexual orientation, age, marital status, veteran status, disability status or any other characteristic protected by law.