Silicon Validation Engineer

United States·Santa Claramid

QA & TestingValidation Engineer

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Quick Summary

Key Responsibilities

Design system-level validation strategies for complex architectures, corner cases, PVT, large-scale behavior,

Requirements Summary

BS/MS in EE/CE (or equivalent experience) 4+ years in silicon bring-up, ASIC validation, or system-level debug Grounding in PVT, timing (STA), signal integrity, power, and high-speed IO (PCIe,

Technical Tools

QA & TestingValidation Engineer

NVIDIA Silicon Co-design Group is seeking a versatile engineer to join the HW ArchDev Methodology team. SCG operates across the full product lifecycle—from early architecture definition through silicon bring-up to production—providing a unique end-to-end perspective on next-generation systems

You define how validation is done. Not how it's been done, how it should be done, for chips that don't exist yet. NVIDIA's HW ArchDev Methodology team sits at a rare intersection: architecture, silicon bring-up, and production, all in one group. We build the validation strategies, automation frameworks, and telemetry systems that determine whether next-generation GPUs and AI accelerators ship on time and at quality. The problems are novel. The stakes are real.

Responsibilities

~1 min read

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Design system-level validation strategies for complex architectures, corner cases, PVT, large-scale behavior, feature interactions
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Build AI-assisted and data-driven validation workflows that improve coverage, debug turnaround, and efficiency
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Profile real workloads: training, inference, HPC, video, and emerging applications
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Deploy automation and telemetry pipelines that scale across products and teams
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Drive silicon bring-up and root-cause debug with reusable, high-leverage methods

Requirements

~1 min read

BS/MS in EE/CE (or equivalent experience)
4+ years in silicon bring-up, ASIC validation, or system-level debug
Grounding in PVT, timing (STA), signal integrity, power, and high-speed IO (PCIe, chip-to-chip)
Understanding of firmware/driver-hardware interaction
Experience or curiosity around data-driven workflows, telemetry, and AI/LLM-assisted development
Thrive in a collaborative environment.

You've applied AI/ML or LLMs to validation, debug automation, or workload analysis, not just mentioned it
You've built infrastructure others still use: pipelines, observability systems, debug tools
You have artifacts: postmortems, test methods, tools, papers, or dashboards that show how you think
You've driven cross-functional work across architecture, firmware, validation, and manufacturing

If you've ever looked at a validation process and redesigned it from first principles, we want to talk!

#LI-Hybrid

Your base salary will be determined based on your location, experience, and the pay of employees in similar positions. The base salary range is 136,000 USD - 218,500 USD.

You will also be eligible for equity and benefits.

Applications for this job will be accepted at least until October 17, 2026.

This posting is for an existing vacancy.

NVIDIA uses AI tools in its recruiting processes.

NVIDIA is committed to fostering an inclusive work environment and proud to be an equal opportunity employer. As we highly value diversity in our current and future employees, we do not discriminate (including in our hiring and promotion practices) on the basis of race, religion, color, national origin, gender, gender expression, sexual orientation, age, marital status, veteran status, disability status or any other characteristic protected by law.