10d ago

Senior Design Verification Engineer - GPU Memory Subsystem

United StatesUnited States·Durhamsenior
Other
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Quick Summary

Key Responsibilities

Actively collaborate with RTL, DV, FV, and Arch teams to then develop and implement design verification strategies for our GPU ASIC memory subsystem IP.

Requirements Summary

BS Degree in CompE, EE, CS, or equivalent experience 5+ years of experience covering the full scope of pre-silicon ASIC verification, including the development of verification strategy,

Technical Tools
Other

NVIDIA has been transforming computer graphics, PC gaming, and accelerated computing for more than 25 years. It’s a unique legacy of innovation that’s fueled by great technology—and amazing people. Today, we’re tapping into the unlimited potential of AI to define the next era of computing. An era in which our GPU acts as the brains of computers, robots, and self-driving cars that can understand the world. Doing what’s never been done before takes vision, innovation, and the world’s best talent. As an NVIDIAN, you’ll be immersed in a diverse, supportive environment where everyone is inspired to do their best work. Come join the team and see how you can make a lasting impact on the world.

 

We're looking for a talented, motivated Senior Design Verification Engineer to join our GPU memory subsystem team in Durham, NC. Looking to join a dynamic team solving complex verification challenges involving caches, coherency, pipelines, and arbitration? This pre-silicon position is perfect for you!

Responsibilities

~1 min read
  • →

    Actively collaborate with RTL, DV, FV, and Arch teams to then develop and implement design verification strategies for our GPU ASIC memory subsystem IP.

  • →

    Perform functional and performance verification using advanced tools and methodologies. Bring your innovative ideas to the table.

  • →

    Gain a deep understanding of this critical IP's micro-architectural design and implementation while continuing to advance your verification skills.

Requirements

~1 min read
  • BS Degree in CompE, EE, CS, or equivalent experience

  • 5+ years of experience covering the full scope of pre-silicon ASIC verification, including the development of verification strategy, test plans, tests, testbench components, regression triage, debug, and coverage closure and experience with industry standard tools

  • Working knowledge of computer architecture fundamentals and their constructs in Verilog/System Verilog

  • Strong analytical thought process and outstanding debug skills.

  • Experience with caches, coherency, complex pipelines, arbiters, or interconnect networks

  • Infrastructure development, use of AI to support design and verification development

  • Testbench development experience, especially with UVM components used in multiple levels of verification

  • Strong programming/scripting experience in Python or C++. Applying suitable algorithms, data structures, and error handling

Your base salary will be determined based on your location, experience, and the pay of employees in similar positions. The base salary range is 136,000 USD - 218,500 USD for Level 3, and 168,000 USD - 264,500 USD for Level 4.

You will also be eligible for equity and benefits.

Applications for this job will be accepted at least until October 11, 2026.

This posting is for an existing vacancy. 

NVIDIA uses AI tools in its recruiting processes.

NVIDIA is committed to fostering an inclusive work environment and proud to be an equal opportunity employer. As we highly value diversity in our current and future employees, we do not discriminate (including in our hiring and promotion practices) on the basis of race, religion, color, national origin, gender, gender expression, sexual orientation, age, marital status, veteran status, disability status or any other characteristic protected by law.

Location & Eligibility

Where is the job
Durham, United States
On-site at the office
Who can apply
US

About this job

Who can apply
United States
Posted
10 days ago
Employer
has 1,607 open jobs on Jobera.

Listing Details

Posted
October 8, 2026
First seen
October 18, 2026
Last seen
October 18, 2026

Posting Health

Days active
-1
Repost count
0
Trust Level
28%
Scored at
October 18, 2026

Signal breakdown

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Senior Design Verification Engineer - GPU Memory Subsystem