19d ago

Senior Director, ATE Test Development

United StatesUnited States·Santa Clarasenior
Other
1 views0 saves0 applied

Quick Summary

Key Responsibilities

Set the vision, roadmap, and operating model guiding ATE creation throughout new product introductions and sustaining production.

Requirements Summary

BS, MS, or PhD in Electrical Engineering, Computer Engineering, or a related field, or equivalent experience. 18+ years of relevant semiconductor experience,

Technical Tools
Other

NVIDIA is seeking a senior engineering leader to define and scale our ATE development strategy for complex silicon products from new product introduction through high-volume manufacturing. This role leads a global organization responsible for production test architecture, hardware and program development, silicon correlation, quality screening, yield enablement, cost-of-test optimization, and test automation. The ideal candidate brings deep semiconductor test expertise, strong interpersonal leadership, and can drive execution across developing, product engineering, manufacturing, reliability, and supplier ecosystems.


Responsibilities

~1 min read
  • →Set the vision, roadmap, and operating model guiding ATE creation throughout new product introductions and sustaining production.
  • →Lead and develop a distributed team composed of managers and senior engineers covering test hardware, program development, characterization, correlation, productization, and data-driven test optimization.
  • →Drive production test readiness for complex devices, including test coverage, guardband strategy, yield learning, defect screening, quality containment, and test cost reduction.
  • →Establish scalable methodologies, standards, release criteria, and quality gates for ATE development and deployment.
  • →Partner closely with architecture, circuit build, test integration, product engineering, system test, reliability, silicon operations, manufacturing, and collaborators outside the company to ensure strong design-to-test alignment.
  • →Lead the strategy for ATE platform selection, vendor engagement, capacity readiness, and capital planning needed to support product ramps.
  • →Use data and analytics to improve silicon correlation, test limits, binning strategies, excursion response, and long-term product quality.
  • →Build a high-performance leadership culture through strong hiring, interpersonal development, succession planning, and multi-functional influence.

Requirements

~1 min read
  • BS, MS, or PhD in Electrical Engineering, Computer Engineering, or a related field, or equivalent experience.
  • 18+ years of relevant semiconductor experience, including 8 + years of management experience. Leading managers and distributed engineering organizations.
  • Deep expertise in ATE development for high-volume silicon, SoC, ASIC, or GPU-class products.
  • Shown success leading organizations through NPI, silicon bring-up, characterization, production ramp, yield improvement, and quality execution.
  • Strong understanding of ATE platforms, test hardware design, test program development, instrumentation, silicon correlation, statistical analysis, and production test methodologies.
  • Consistent track record to partner across design, DFT, product engineering, failure analysis, reliability, manufacturing, and supplier or OSAT ecosystems.
  • Experience owning roadmaps, budgets, staffing plans, and operational priorities for large-scale engineering organizations.
  • Strong executive communication skills with the ability to influence senior collaborators and drive alignment across technical and business teams.

  • Experience with GPU, AI, networking, or other high-performance compute products.
  • Track record of reducing test cost while improving outgoing quality and production scalability.
  • Strong background in test automation, data infrastructure, and improvement guided by data insights.
  • Experience building and scaling global test-development organizations across multiple sites and external partners.
  • Familiarity with system-level test, product binning, performance and power optimization, or silicon operations workflows.

With competitive salaries and a generous benefits package, NVIDIA is widely considered to be one of the technology world’s most desirable employers. We have some of the most forward-thinking and hardworking people in the world working for us. This role presents an opportunity to have a wide impact at NVIDIA by improving the factory planning function. Are you creative, hard-working, dedicated, and determined? Do you love a challenge? If so, we want to hear from you!

Your base salary will be determined based on your location, experience, and the pay of employees in similar positions. The base salary range is 320,000 USD - 483,000 USD.

You will also be eligible for equity and benefits.

Applications for this job will be accepted at least until October 11, 2026.

This posting is for an existing vacancy. 

NVIDIA uses AI tools in its recruiting processes.

NVIDIA is committed to fostering an inclusive work environment and proud to be an equal opportunity employer. As we highly value diversity in our current and future employees, we do not discriminate (including in our hiring and promotion practices) on the basis of race, religion, color, national origin, gender, gender expression, sexual orientation, age, marital status, veteran status, disability status or any other characteristic protected by law.

Location & Eligibility

Where is the job
Santa Clara, United States
On-site at the office
Who can apply
US

About this job

Who can apply
United States
Posted
19 days ago
Employer
has 3,026 open jobs on Jobera in 29 countries.

Listing Details

Posted
October 8, 2026
First seen
October 18, 2026
Last seen
October 27, 2026

Posting Health

Days active
8
Repost count
0
Trust Level
19%
Scored at
October 27, 2026

Signal breakdown

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Senior Director, ATE Test Development