CAD Developer, IR, Timing and Physical Design Optimization

ASIC-PD team is hiring both junior and senior engineers, whose work scope is physical design from RTL to GSDII: design quality check, synthesis, formal check, partitioning, constraint (for both design and process), async check, timing analysis/fixing/signoff, also all related flow. Join us, you will work together with expertise in all these areas; you will not only work for physical application, but also drive physical friendly design with all related teams: ASIC/P&R/DFT/SI/ARCH etc.; you will work for the most advanced process/technology, the biggest chip in the world.

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  Invent and optimize new methods for increasing chip frequency while minimizing power consumption across a suite of internal optimization tools. 

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  Improve algorithms (in C++) for IR drop optimization, simulation

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  As with any software engineering team, we do write a lot of code, but this is broader than a typical CAD or EDA role. Instead, we as a team own the whole process from discovery and invention of new optimization opportunities, to developing solutions and working directly inside design teams to facilitate deployment.

• BS, MS, PhD in Electrical Engineering or Computer Science or equivalent experience

• Minimum 2+ years of relevant experience in CAD software and VLSI hardware design

• Strength in both CAD software and VLSI design

• Understanding of VLSI IR drop optimization or simulation and related concepts, including constraints, corner, CCSP, FSDB etc.

• Demonstrated ability in software development using C++

• Strong communication and interpersonal skills

• Familiarity with RedHawk and typical design flows written in Perl, Tcl, and Python.

• C++14 or newer experience, such as lambdas and concurrency

• Experience in high-performance software design including multithreading, distributed computing, efficient memory, and I/O use, etc.

• Experience in IR drop optimization, calculation