1mo ago

DFT Engineer (RDSS Intern) - 2027

2 Locationsentry
Other
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Quick Summary

Key Responsibilities

Verify our custom IP macros. Collaborate with Design, Integration and TE teams to determine verification scope, develop strategies, implement test planning, and verify designs at IP level,

Requirements Summary

Master degree of Electrical Engineering/Computer Engineering/Computer Science Strong debugging and analytical skills with RTL/Gate-level design tracing(Verdi) and verification simulation tool(VCS).

Technical Tools
Other

By submitting your resume, you’re expressing interest in our 2027 RDSS (Research and Development Substitute Services) program. Please confirm your eligibility with the local district office before applying the role.

NVIDIA is seeking phenomenal engineers to improve our verification methodology, so we can validate the world’s largest design efficiently. This position offers the opportunity to have real impact in a dynamic, technology-focused company impacting product lines ranging from consumer graphics to self-driving cars and the growing field of artificial intelligence.

 

We have crafted a team of extraordinary people stretching around the globe, whose mission is to push the frontiers of what is possible today and define the platform for the future of computing. We are now looking for a DFT Engineer in our Taiwan, Taipei/Hsinchu Office!

Responsibilities

~1 min read
  • →

    Verify our custom IP macros.

  • →

    Collaborate with Design, Integration and TE teams to determine verification scope, develop strategies, implement test planning, and verify designs at IP level, cluster level, and full chip level

  • →

    Collaborate with CAD team to optimize & smooth our simulation flow

  • →

    Generating test patterns and perform silicon bring-up

Requirements

~1 min read
  • Master degree of Electrical Engineering/Computer Engineering/Computer Science

  • Strong debugging and analytical skills with RTL/Gate-level design tracing(Verdi) and verification simulation tool(VCS).

  • Familiarity with SOC basic architecture (clock, reset, power rail, IO pad, package)

  • Understanding of Design for Testing including Scan/ATPG/BIST/JTAG is a plus

  • Skills of Python/Perl/Tck/C/C++ is a plus

  • Fluent English communication is required

Location & Eligibility

Where is the job
Not specified
Location terms not specified
Who can apply
Same as job location

About this job

Posted
38 days ago
Employer
has 3,391 open jobs on Jobera in 29 countries.

Listing Details

Posted
September 29, 2026
First seen
October 18, 2026
Last seen
November 6, 2026

Posting Health

Days active
19
Repost count
0
Trust Level
11%
Scored at
November 7, 2026

Signal breakdown

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DFT Engineer (RDSS Intern) - 2027