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Research Fellow (Digital IC design and EDA)

Postdoctoral ResearcherLaboratory & Life Sciences
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Quick Summary

Key Responsibilities

Conduct independent and collaborative research on open-source processor architectures and hardware accelerators, including RISC-V based designs. Design, implement,

Requirements Summary

A completed PhD in Electrical Engineering, Computer Engineering, Computer Science, or a closely related discipline. Strong research expertise in RISC-V architecture, processor microarchitecture,

Technical Tools
Postdoctoral ResearcherLaboratory & Life Sciences

School of Electrical and Electronic Engineering is one of the founding Schools of the Nanyang Technological University. Built on a culture of excellence, the School is renowned for its high academic standards and research.  With over 3,000 undergraduates students and 2,000 graduate students it is one of the largest EEE schools in the world and ranks 4th in the field of Electrical & Electronic Engineering in the 2025 QS World University Rankings by Subjects.

Today, the School has become one of the world’s largest engineering schools that nurtures competent engineers and researchers. Each year, the School graduates over a thousand students who are ready to take on great ambitions and challenges.

For more details, please view: https://www.ntu.edu.sg/eee

We are looking for a Research Fellow to focus on open-source processor and accelerator architectures. The role focuses on advancing research in integrated circuit (IC) design and electronic design automation (EDA), with particular emphasis on RISC-V based processors, AI accelerators, and open-source hardware toolchains. The Research Fellow contributes to the University’s mission by conducting high-impact research, developing innovative hardware architectures and design methodologies, and disseminating research outcomes through publications, collaborations, and open-source contributions.

Responsibilities

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    Conduct independent and collaborative research on open-source processor architectures and hardware accelerators, including RISC-V based designs.

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    Design, implement, and evaluate digital ICs using Verilog/SystemVerilog and related hardware description languages.

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    Develop and optimize EDA workflows for processor and accelerator design, verification, and physical implementation using open-source tools.

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    Explore architecture-algorithm co-design for machine learning and AI acceleration.

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    Perform performance, power, and area (PPA) analysis of processor and accelerator designs.

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    Publish research findings in top-tier conferences and journals and contribute to open-source hardware and EDA communities.

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    Supervise and mentor PhD students, junior Research Assistants, and Master students.

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    Collaborate with faculty members, graduate students, and external partners, and support research project execution and reporting.

Requirements

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  • A completed PhD in Electrical Engineering, Computer Engineering, Computer Science, or a closely related discipline.

  • Strong research expertise in RISC-V architecture, processor microarchitecture, and AI accelerators.

  • Experience with ASIC design methodologies and open-source IC design and EDA tools.

  • Proven experience in digital hardware design using Verilog/SystemVerilog or equivalent HDLs.

  • Sound knowledge of machine learning algorithms and their hardware implementation considerations.

  • Demonstrated ability to conduct independent, high-quality research and publish in reputable venues.

  • Demonstrated ability to lead research projects, supervise researchers, and mentor junior staff.

  • Strong analytical and problem-solving skills, with the ability to work independently and collaboratively.

  • Good written and oral communication skills.

We regret to inform you that only shortlisted candidates will be notified.

Hiring Institution: NTU

Location & Eligibility

Where is the job
Singapore
On-site within the country
Who can apply
SG

About this job

Who can apply
Singapore
Posted
Today
Employer
has 733 open jobs on Jobera.

Listing Details

First seen
October 18, 2026
Last seen
October 18, 2026

Posting Health

Days active
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Trust Level
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Scored at
October 18, 2026

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Research Fellow (Digital IC design and EDA)