Senior SOC Design For Test Engineer

NXP Semiconductors is seeking an experienced and motivated Senior Design For Test (DFT) Engineer to join the AI and Chip Engineering (ACE) team. In this role, you will define, implement, verify, and support advanced DFT solutions for complex SoC products developed in leading-edge semiconductor technologies for Automotive and Industrial applications.

Working closely with design, verification, product engineering, and manufacturing teams, you will contribute to the delivery of cost-effective, high-quality DFT architectures and manufacturing test solutions that ensure robust product quality and test coverage.

• →Define and implement Digital Design For Test (DFT) architectures and solutions at IP, subsystem, and SoC level based on product requirements and specifications.
• →Develop and integrate DFT features including Scan, ATPG, Memory BIST, Logic BIST, JTAG, and related test structures.
• →Align DFT implementation across SoC platforms and IP blocks to ensure efficient, scalable, and high-quality test solutions.
• →Develop and execute ATPG patterns to achieve target fault coverage for Stuck-At, Transition Delay, Memory BIST, and Logic BIST testing.
• →Perform DFT verification, simulations, and validation activities to ensure the correctness and effectiveness of implemented test solutions.
• →Collaborate with design, verification, physical design, and product engineering teams throughout the development cycle to ensure testability requirements are met.
• →Support silicon bring-up activities and participate in post-silicon evaluation to ensure manufacturing test patterns are operational from first silicon.
• →Analyze test results, debug failures, identify root causes, and drive yield and quality improvements.
• →Work with manufacturing and ATE teams to enable efficient production test flows.
• →Evaluate and adopt new DFT methodologies, tools, and industry best practices to improve test quality, coverage, and cost efficiency.
• →Document DFT architecture, implementation details, verification strategies, and test plans.
• →Provide technical leadership and mentorship to junior engineers when appropriate.

• Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, Microelectronics, or a related field.
• Strong experience in DFT design and verification for complex ASIC or SoC products.
• Solid understanding of DFT methodologies including: Scan DesignATPGMemory BISTLogic BISTJTAG / Boundary Scan
• Experience with industry-standard DFT tools such as Synopsys TestMAX, Cadence Modus, or Siemens Tessent.
• Good understanding of digital design fundamentals, ASIC/SoC development flows, and semiconductor manufacturing test concepts.
• Experience with Verilog/SystemVerilog.
• AI Driven programming or scripting skills using TCL, Python, Perl, or similar languages.
• Strong analytical and problem-solving skills.
• Effective communication and collaboration skills in a multidisciplinary environment.

• Experience supporting silicon bring-up and post-silicon debug activities.
• Experience in driving DFT conception and development with AI tools.
• Familiarity with ATE test development and manufacturing test flows.
• Knowledge of advanced semiconductor process technologies.
• Experience working on Automotive or Industrial semiconductor products.