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Lead Engineer - SoC Design Verification

IndiaIndia·Punelead
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Quick Summary

Key Responsibilities

Develop and own SoC-level and/or IP-level verification suites with coverage goals. Responsible for executing verification plan according to the product specification and verification

Technical Tools
Other

We are seeking an experienced Design Verification Engineer with 6+ years of expertise for execution of complex SoCs. The ideal candidate will have deep knowledge of ARM-based microcontrollers, low-power design verification, and experience with multiple interfaces and security IPs. This is a hands-on role requiring strong technical skills and collaboration in a fast-paced environment.

Responsibilities

~1 min read
  • →Develop and own SoC-level and/or IP-level verification suites with coverage goals.
  • →Responsible for executing verification plan according to the product specification and verification requirements defined by product architects.
  • →Responsible for developing, debugging and running UVM based verification environment for RTL/netlist simulation.
  • →Define and develop test cases in an appropriate verification framework. Create stimulus and assertions, run simulation, debug test cases on the design models (RTL, power aware RTL, gate level, FPGA, Emulation platform), run regression, collect and analyze code/functional coverage
  • →Drive DV closure on diverse IPs and subsystems, ensuring maximum coverage and quality.
  • →Familiar with both SoC-level and IP-level verification environments.
  • →Collaborate with the team in developing and improving flows for maximum reuse and efficiency.
  • →Mentor junior team members while actively collaborating with design teams for issue resolution and sign-off.

Requirements

~1 min read
  • Experience: 5-12 years in SoC/IP verification with participation in successful tape-outs of SoCs.
  • Technical Skills:
    • Strong expertise in ARM-based microcontrollers and SoC-level verification, including C based DV.
    • Proficiency in Verilog, SystemVerilog, UVM, and constrained-random verification.
    • Familiarity with EDA tools (Synopsys VCS, Cadence Xcelium).
    • Experience with low-power verification (UPF) is a plus.
    • Gate-level simulations and power-aware simulations is a plus.
    • Good working knowledge of assertions (SVA) and functional coverage.
    • Verification of multiple interfaces: SPI, I²C, UART, USB, PCIe, Ethernet, CAN, eSPI is desirable.
    • Knowledge of Flash memory and security IPs is nice to have.
    • Any experience with common Analog IPs in microcontroller design (ADC, DAC, PLLs) is an added advantage.
  • Soft Skills:
    • Comfortable working in a fast-paced environment.
    • Strong team player with excellent communication skills.
  • Education: Bachelors or Master’s in Microelectronics, Electronics, Electrical Engineering


More information about NXP in India...

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Location & Eligibility

Where is the job
Pune, India
On-site at the office
Who can apply
IN

About this job

Who can apply
India
Posted
Today
Employer
has 675 open jobs on Jobera in 11 countries.

Listing Details

First seen
October 18, 2026
Last seen
October 18, 2026

Posting Health

Days active
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Trust Level
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Scored at
October 18, 2026

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Lead Engineer - SoC Design Verification