Principal Post-Silicon Validation Engineer

Astera Labs is looking for a Principal Post-Silicon Validation Engineer to take our connectivity silicon from first-silicon bring-up to production-ready. You will own the validation strategy for high-speed interconnect products, characterize real silicon in the lab, and drive root-cause analysis of the toughest system-level issues.

As AI workloads scale into rack-level infrastructure, every link has to perform flawlessly. Your work will directly shape the quality, performance, and time-to-market of the products that connect the world's most advanced AI platforms, in a hyper-growth company where your technical judgment carries real weight.

• Architect and drive end-to-end post-silicon validation plans, from first-silicon bring-up through characterization and production release
• Define test strategies, coverage goals, and exit criteria in partnership with design, architecture, and product teams
• Lead lab bring-up of new silicon, including board, firmware, and software readiness

• Debug complex silicon, firmware, and system-level failures to root cause across the hardware/software boundary
• Characterize high-speed serial link performance, including margining, signal integrity, and compliance, across process, voltage, and temperature
• Partner with design and DFT teams to feed findings back into current and future product generations

• Develop scalable validation automation frameworks and test content using Python and C/C++
• Build and improve lab infrastructure, test benches, and data analysis flows to increase validation throughput
• Analyze large validation datasets to identify trends, outliers, and risks early

• Mentor engineers and set best practices for validation methodology across the team
• Collaborate with customers and Field Applications Engineers to reproduce and resolve system-level issues

• Bachelor's degree in Electrical Engineering, Computer Engineering, or a related field
• 8-12 years of experience in post-silicon validation, silicon bring-up, or hardware characterization
• Hands-on experience with high-speed serial interfaces such as PCIe, including a strong understanding of the physical layer
• Proficiency in lab equipment, including oscilloscopes, BERTs, protocol analyzers, and power supplies
• Strong scripting and programming skills in Python and/or C/C++ for test automation
• Proven ability to debug complex hardware and firmware issues to root cause

• Master's degree or PhD in Electrical Engineering, Computer Engineering, or a related field
• Experience with PCIe Gen 5 or Gen 6, Ethernet, or retimer products
• Experience with SerDes characterization, equalization tuning, and link margining
• Track record of taking multiple products from first silicon to volume production
• Strong cross-functional communication skills and the ability to lead without direct authority

Salary range is $207,000 to $230,000 depending on experience, level, and business need. This role may be eligible for discretionary bonus, incentives and benefits.