18d ago

Physical Verification Engineer

2 Locationsmid
Other
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Quick Summary

Key Responsibilities

Run and analyze physical verification checks such as DRC, LVS, and other tapeout-quality signoff checks. Debug physical verification violations and partner with design teams to drive clean closure.

Requirements Summary

B.Sc. or M.Sc. in Electrical Engineering, Computer Engineering, or equivalent experience. 2+ years of experience in physical verification, backend implementation, or VLSI signoff.

Technical Tools
Other

NVIDIA is seeking a Physical Verification Engineer to help ensure our ASIC and SoC designs are clean, correct, and ready for tapeout. This role focuses on physical verification quality across layout data, connectivity, and manufacturing rule compliance. You will work closely with physical design, custom layout, and methodology teams to run verification flows, debug issues, and improve signoff robustness. This is an excellent opportunity for an engineer who enjoys detailed analysis and high-impact signoff work.


Responsibilities

~1 min read
  • →Run and analyze physical verification checks such as DRC, LVS, and other tapeout-quality signoff checks.
  • →Debug physical verification violations and partner with design teams to drive clean closure.
  • →Review layout, netlist, and runset interactions to identify root causes and recommend fixes.
  • →Support full-chip and block-level verification readiness across implementation milestones.
  • →Improve physical verification flow quality, turnaround time, and automation.
  • →Collaborate with methodology, CAD, and foundry-facing teams on rule interpretation and signoff quality.

Requirements

~1 min read
  • B.Sc. or M.Sc. in Electrical Engineering, Computer Engineering, or equivalent experience.
  • 2+ years of experience in physical verification, backend implementation, or VLSI signoff.
  • Strong understanding of DRC, LVS, antenna, and layout verification concepts.
  • Hands-on experience with tools such as Calibre, ICV, Pegasus, or equivalent physical verification tools.
  • Ability to debug verification issues across layout, extracted views, and netlist connectivity.
  • Scripting ability in Tcl, Perl, Python, or shell for automation and debug.
  • Strong collaboration skills and attention to detail.

  • Experience with advanced-node signoff and foundry rule decks.
  • Familiarity with stream-out/OASIS or GDSII generation and tapeout readiness flows.
  • Experience improving PV automation, dashboards, or regression infrastructure.

Widely considered to be one of the technology world’s most desirable employers, NVIDIA offers highly competitive salaries and a comprehensive benefits package. As you plan your future, see what we can offer to you and your family www.nvidiabenefits.com/

Location & Eligibility

Where is the job
Not specified
Location terms not specified
Who can apply
Same as job location

About this job

Posted
18 days ago
Employer
has 3,400 open jobs on Jobera in 29 countries.

Listing Details

Posted
October 20, 2026
First seen
October 21, 2026
Last seen
November 7, 2026

Posting Health

Days active
16
Repost count
0
Trust Level
18%
Scored at
November 7, 2026

Signal breakdown

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Physical Verification Engineer