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Trainee Engineer

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Quick Summary

Key Responsibilities

Assist in developing, maintaining, and enhancing block-level and chip-level simulation testbenches (TB) UVM Architecture: Write scalable verification components, including drivers, monitors,

Requirements Summary

Bachelor’s or master’s degree in Electronics Engineering, Computer Engineering, Computer Science, or a related field (Graduation date within the last 12 months).

Technical Tools
Other
#WeAreIn to make sure that our circuits are designed to perfection. Are you in? We are seeking a highly motivated, talented individual to join our Silicon Engineering team as a Trainee Engineer - Digital Design Verification. In this role, you will work on Graphics /Security IP, helping to ensure the functional correctness of complex, next-generation architecture. You will learn from industry experts and gain hands-on experience building advanced simulation and emulation testbenches using industry-standard methodologies .  Your role Key responsibilities in your new role Testbench  Development: Assist in developing, maintaining, and enhancing block-level  and chip-level simulation testbenches (TB) UVM  Architecture: Write scalable verification components, including drivers,  monitors, predictors, and scoreboards using SystemVerilog (SV) and UVM.   Emulation  Platforms: Collaborate with senior engineers to bring up emulation  testbenches for hardware-accelerated verification and pre-silicon  validation.   Graphics  IP Verification: Learn the intricate architecture of Graphics IPs  (pipelines, shaders, or memory controllers) and map out comprehensive  verification plans.   Debug  & Coverage: Run regressions, debug hardware failures using waveform  viewers, and write functional coverage covergroups to achieve 100% verification closure. Your profile Qualifications and skills to help you succeed  Education:  Bachelor’s or master’s degree in Electronics Engineering, Computer  Engineering, Computer Science, or a related field (Graduation date within     the last 12 months).   Languages:     Strong foundational knowledge of SystemVerilog (SV).   Methodology:  Exposure to UVM (Universal Verification Methodology) through university  coursework, lab projects, or internships.   Core  Concepts: Solid understanding of digital logic design, computer  architecture, and FIFO/arbitration mechanisms.  Scripting:  Basic proficiency in scripting languages like Python, Perl, or Bash for  automation. Preferred Qualifications (Bonus) Prior  internship experience in ASIC/FPGA design or verification. Direct  project experience involving Graphics IP , GPU architectures, or  high-throughput data pipelines. Familiarity  with hardware emulation platforms (e.g., Palladium, Zebu, Veloce)  or FPGA prototyping. Experience  with EDA tools from Synopsys, Cadence, or Siemens (e.g., VCS, Questa,  Xcelium) #WeAreIn for driving decarbonization and digitalization. As a global leader in semiconductor solutions in power systems and IoT, Infineon enables game-changing solutions for green and efficient energy, clean and safe mobility, as well as smart and secure IoT. Together, we drive innovation and customer success, while caring for our people and empowering them to reach ambitious goals. Be a part of making life easier, safer and greener. Are you in? We are on a journey to create the best Infineon for everyone. We strive to create the best Infineon for everyone by embracing diversity and inclusion. We welcome applicants for who they are and offer a workplace built on trust, openness, respect and equal opportunity.  Our hiring decisions are based on skills and experience. Even if you don’t meet every requirement, we encourage you to apply. Please let your recruiter know if you need any accommodations during the interview process. Learn more about our various contact channels and about Diversity & Inclusion at Infineon.

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Where is the job
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About this job

Posted
Today
Employer
has 68 open jobs on Jobera.

Listing Details

Posted
November 3, 2026
First seen
November 3, 2026
Last seen
November 3, 2026

Posting Health

Days active
0
Repost count
0
Trust Level
56%
Scored at
November 3, 2026

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Trainee Engineer