SoC Verification Engineer - Design for Debug/Design For Test
Quick Summary
- Validation of Design for Debug features (e.g. low and high-bandwidth signal tracing and event triggering) using simulation, emulation, and/or FPGA- Validation of Design for Test features like TAP,
Minimum Qualifications: Candidate must have either a BS or MS in Computer Science, Computer Engineering or Electrical Engineering.
Come join Intel's Design Development Group organization as an SOC Validation engineering focused on Design for Debug (DFD) and Design for Test ( DFT ).
As a member of the product team, you will work firsthand with multi-function teams/sites, implementing and validating state-of-the-art debug solutions appropriate for new and existing technology in the product. In this role you will be working as part of a pre-silicon validation team for future Intel SoCs or IPs, focusing on debug validation. You will be working with pre-silicon and post -silicon validation teams to improve debug features and tools suites. You will also work closely with post-silicon validation SW teams on debug tool validation and silicon enabling. You will be pioneering new debug tools and flows, reviewing and publishing architectural specs and supporting next-generation silicon enabling on system platforms.
Your responsibilities will include but not be limited to:
Requirements
~1 min read*
ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.Location & Eligibility
About this job
- Who can apply
- India
- Posted
- Today
Listing Details
- Posted
- November 13, 2026
- First seen
- November 13, 2026
- Last seen
- November 13, 2026
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- Trust Level
- 56%
- Scored at
- November 13, 2026
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