Advanced Package Engineer, Principal

Location: San Jose, CA (On-site). 

About the Role 

Astera Labs is seeking Advanced Packaging Engineer, Principal to lead advance packaging R&D for next-generation photonics products for scale up and scale out AI infrastructure applications. This is a senior individual contributor role focused on setting technical direction and driving packaging technology development for NPO and CPO products. 

Responsibilities 

• Lead R&D for advanced packaging of optical chips, including 2.1D, 2.5D, and 3D integration. 

• Define and optimize wafer-level, panel-level, or die-level packaging process flows. 

• Drive EIC-to-PIC integration and broader optical device integration efforts. 

• Select and qualify packaging materials for advanced packaging. 

• Partner with OSAT, tool vendors, and material suppliers to drive equipment, process, and materials development. 

• Characterize and continuously improve yield, reliability, and process capability for NPO and CPO packages. 

• Develop and maintain packaging PDKs and design rules for NPO and CPO products. 

Basic Qualifications 

• B.S., M.S., or Ph.D. in Electrical Engineering, Materials Science, Mechanical Engineering, or a related field. 

• 8+ years of experience in semiconductor or advanced packaging engineering, with demonstrated technical leadership. 

• Deep expertise in advanced packaging processes, including 2.5D/3D integration, flip-chip, hybrid bonding, Cu pillar, TSV, RDL, and overmold across wafer-, panel-, and die-level flows. 

• Experience with silicon photonics chip packaging and EIC/PIC integration. 

• Hands-on experience with advanced packaging materials, including underfill, molding compounds, dielectrics, adhesives, or optical-grade encapsulants. 

• Proven track record of equipment and process qualification with OSAT or tool suppliers. 

• Experience with PDK development and packaging design rule authoring. 

• Strong foundation in yield analysis, reliability characterization, and process capability methodologies such as Cpk and SPC. 

Preferred Qualifications 

• Hands-on experience with CPO or NPO product development. 

• Experience with optical coupling or waveguide alignment for photonic integration. 

• Familiarity with photonics chip design and photonics devices 

• Familiarity with DFM and DFT for advanced packaging.

Salary range is $205,000 to $255,000 depending on experience, level, and business need. This role may be eligible for discretionary bonus, incentives and benefits.