Advanced Packaging Lead/Architect

Bitdeer is a world-leading technology company for Bitcoin mining and AI cloud.

Bitdeer is committed to providing comprehensive Bitcoin mining solutions for its customers. Apart from designing industry-leading ASIC chips and manufacturing mining rigs, the Group handles complex processes involved in computing across the value chain. This includes equipment procurement, transport logistics, datacenter design and construction, equipment management, and network and facility operations. Bitdeer also offers advanced cloud capabilities to customers with a high demand for artificial intelligence.

Headquartered in Singapore, Bitdeer operates globally with a diversified 3 GW energy portfolio, and deploys Bitcoin mining and HPC datacenters in the United States, Bhutan, Norway, Canada, Malaysia, and Ethiopia.

Lead chip packaging design and simulation from architecture through production. Align silicon, memory, board, cooling and supplier teams to meet performance, reliability, cost and schedule targets. Own multiphysics analysis, technical decisions and design signoff.

• →Define packaging roadmaps and product architectures, including structures, die placement, substrate stack-ups, interconnects and power delivery. Assess manufacturability, cost, yield and delivery risks.
• →Lead chip–package–board co-design. Review bump/ball maps, layout, routing and manufacturing constraints; drive design closure and release.
• →Lead signal integrity (SI), power integrity (PI), thermal and thermomechanical analysis. Define models, boundary conditions, design budgets, margins and signoff criteria.
• →Establish simulation-to-measurement validation. Coordinate prototype testing, model correlation and root-cause analysis; resolve electrical, thermal, structural and reliability issues.
• →Own technical interfaces with foundries, assembly/test partners and substrate vendors. Work with product, test and quality teams on pilot builds, qualification, yield improvement and production ramp.
• →Establish design reviews, version control, engineering change and documentation practices. Identify risks and drive technical trade-offs and decisions across teams.
• →Recruit, develop and manage packaging design and simulation engineers. Define responsibilities, project plans and resources; build reusable methods, models and design guidelines.

• →A culture that values authenticity and diversity of thoughts and backgrounds;
• →An inclusive and respectable environment with open workspaces and exciting start-up spirit;
• →Fast-growing company with the chance to network with industrial pioneers and enthusiasts;
• →Ability to contribute directly and make an impact on the future of the digital asset industry;
• →Involvement in new projects, developing processes/systems;
• →Personal accountability, autonomy, fast growth, and learning opportunities;
• →Attractive welfare benefits and developmental opportunities such as training and mentoring.

• Required qualifications:
  
  • Bachelor’s degree or above in electrical engineering, microelectronics, materials, mechanical engineering or a related field; 10+ years of relevant chip packaging design or development experience.
  • Ownership of at least one complex packaging project from architecture through design, validation and volume production, with demonstrable decisions and results.
  • Knowledge of flip-chip/FC-BGA, substrate design, materials and assembly processes, including trade-offs across high-speed interconnects, power delivery, cooling and reliability.
  • Hands-on depth in at least one area: package design, SI/PI, thermal or thermomechanical analysis, with the ability to guide multidisciplinary analysis and design signoff.
  • Team leadership, cross-functional collaboration and supplier technical management experience. Ability to use relevant EDA/simulation tools for analysis or review, with effective technical communication and documentation in English.

• Preferred qualifications:
  • Advanced packaging experience in 2.5D/3D design, simulation or production is preferred, including relevant work on chiplets, heterogeneous integration, interposers, RDL, TSVs, microbumps or hybrid bonding.
  • Experience with CPUs, GPUs, switch chips, high-performance ASICs, large or high-power packages, or familiarity with advanced packaging and substrate supply chains.