Advanced ASIC FPGA Engineer- (Sign-on Bonus Available)

Bachelor’s degree in Electrical or Computer Engineering, or a related Science, Engineering, Technology or Mathematics field. Also requires 5+ years of job-related experience, or a Master's degree and 3 years of job-related experience.

 

Candidates must be able to obtain a U.S. Department of Defense TS/SCI security clearance within a reasonable amount of time from date of hire. Applicants selected will be subject to a U.S. Government security investigation and must meet eligibility requirements for access to classified information. Due to the nature of work performed within our facilities, U.S. citizenship is required.

• Ability to generate micro architecture and detailed design approaches

• Proficient in async design principals, timing closure, and constraint generation

• Proficiency in HDL (VHDL/Verilog)
• Proficiency in scripting languages such as Tcl, Python, or Perl
• Effective communication, presentation skills, and high proficiency in technical problem solving
• U.S. citizenship with the ability to obtain and maintain a Secret security clearance

• Leads technical tasks or small projects
• Understanding of high reliability design principals
• Experience with Xilinx and Microchip FPGAs along with associated tools (ISE, Vivado, Libero)
• Experience with synthesis tools (Precision, Synplify)
• Experience with verification tools (QuestaSim/UVM)
• Experience with clock-domain-crossing tools (Questa CDC)
• Experience with lab bring-up and debug (Oscilloscope, Logic Analyzer, ChipScope)
• Active DoD Secret Clearance or higher

Workplace Options:This position is fully on-site or hybrid/flex, as mutually agreed.While on-site, you will be a part of the Scottsdale, AZ team. Learn more at https://gdmissionsystems.com/about-us/major-locations/scottsdale

Key Words:   Verification, ASIC, FPGA, SystemVerilog, Verilog, Assertions (SVA), OVM, UVM, Digital Signal Processing (DSP), functional coverage, constrained random, formal verification, constrained random testing 

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The individual will be responsible for and participate in the ASIC/FPGA product life cycle (requirements, design, implementation, and test).  Must be knowledgeable in VHDL and/or Verilog RTL coding and be proficient in micro-architecture design.  Successful candidates will have an understanding of digital design concepts and proficient in the digital design tool flow (synthesis, timing, place and route, and in system debug). 

 

This candidate must have an ability to operate in a team environment and collaborate across the different teams as required to accomplish the design goals.  Must have strong written and oral communication skills.

 

This estimate represents the typical salary range for this position based on experience and other factors (geographic location, etc.). Actual pay may vary. This job posting will remain open until the position is filled.

USD $122,785.00 - USD $136,215.00 /Yr.

General Dynamics Mission Systems (GDMS) engineers a diverse portfolio of high technology solutions, products and services that enable customers to successfully execute missions across all domains of operation. With a global team of 12,000+ top professionals, we partner with the best in industry to expand the bounds of innovation in the defense and scientific arenas. Given the nature of our work and who we are, we value trust, honesty, alignment and transparency. We offer highly competitive benefits and pride ourselves in being a great place to work with a shared sense of purpose. You will also enjoy a flexible work environment where contributions are recognized and rewarded. If who we are and what we do resonates with you, we invite you to join our high-performance team!

Equal Opportunity Employer / Individuals with Disabilities / Protected Veterans