Senior CPU Performance Architect

The Role and Impact
As a CPU Performance Architect, you will play a pivotal role in shaping the future of Intel's cutting-edge CPU designs, driving innovation across high-performance computing and extreme low-power products. This position offers the unique opportunity to be at the forefront of technological advancements, defining and delivering architecture specifications that directly impact Intel's success and industry leadership. Your contributions will influence the performance, scalability, and efficiency of CPUs that serve diverse market segments, from enterprise solutions to edge computing devices.

Through collaboration with cross-functional teams, you will invent novel microarchitectural approaches, overcome bottlenecks, and refine designs to meet stringent constraints and evolving demands. Your work will enable Intel to consistently push boundaries and deliver CPUs that meet and exceed customer expectations.

Key Responsibilities

• Develops and drives end-to-end CPU microarchitecture specifications for highly optimized, modular, and scalable CPU based on hardware features, requirements, and interoperability of hardware and software throughout the product life cycle.
• Evaluates feasibility tradeoffs, explores, and defines new approaches and novel microarchitectures for CPU.
• Models CPU performance and power characteristics and analyzes the bottlenecks of current performance features on workloads that reflect CPU future usage.
• Collaborates with architects, design, verification, and validation engineers during the execution of the project.
• Delivers definition of new microarchitecture and finds mitigations for issues that arise during feature implementation to improve the overall design of CPU and overcome bottlenecks and constraints.
• Participates in the debug and fixing of performance miscorrelation between RTL and\or silicon results against the performance model.
• Candidate must have experience in designing high performance CPUs and should be an expert in at-least one or multiple domains across the CPU (Branch Prediction, Fetch/Decode, Rename/Allocation, Reservation Stations/Execution, Memory Subsystem or Prefetchers and its interactions with Uncore).
• Experience in debugging microarchitecture and simulation issues.
• Strong background in microarchitecture/RTL/logic development.
• Proven ability to resolve complex problems, applying analytical and technical skills effectively.

Minimum Qualifications

• The candidate must have a Master's Degree with at 10+ years of experience or a PhD (with dissertation within a general CPU performance domain) with 6+ years of experience working within a high performance, high frequency ARM or x86 CPU performance team.
• Candidate must have at 8+ years of continuous work within cycle accurate C++ CPU performance simulators

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