Senior Design Verification Engineer

• Own verification planning and execution for key IP features across IP and subsystem integration points
• Build scalable verification environments and targeted test plans with reusable test benches, checkers, VIPs, and behavioral models
• Collaborate closely with architecture, design, and software teams from specification through bringup; contribute across role boundaries when needed to unblock progress and maintain execution quality
• Drive ownership of multiple critical blocks and verification components; take full responsibility for functional signoffs and achievement of performance and power metrics
• Lead IP delivery to multiple customers while ensuring technical excellence; balance competing requirements, schedules, and resources across teams
• Drive convergence of simulation and formal verification into unified bug hunting and coverage closure strategies; evaluate and adopt emerging methodologies including ML-driven verification flows
• Mentor and develop verification engineers; establish verification best practices and raise team-level execution quality
• Comfortable using AI-assisted development tools as part of everyday workflow; track record of delivering reusable, configurable verification collateral

• Excellent communication and organizational skills with a track record of delivering high-quality silicon on schedule; able to adapt as tools, methodologies, and role definitions evolve

The Minimum qualifications are required to be initially considered for this position.  Minimum qualifications listed below would be obtained through a combination of industry relevant job experience, internship experience and / or schoolwork/classes/research. The preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.

• Bachelor of Science Degree in Electrical or Computer Engineering, Computer Science, or in a STEM related field
• 10+ years of experience in design verification (DV); with extensive background in IP DV, and subsystem and SoC-level verification
• Experience in interconnects, caches, and memory subsystems, including multiple bus protocols such as AMBA (CHI, ACE, AXI), PCIe, UCIe, and CXL; cache coherency and memory consistency models
• Experience in verification of global functions including debug, trace, clock and power management, RAS, QoS, and security feature
• Experience in simulation and formal verification methodologies including UVM, SVA, ABV, and co-simulation; proficiency in low-power verification techniques, HDL/verification languages, and industry-standard EDA tools
• Hands-on coding experience across SystemVerilog/UVM, C/C++, Python, and build systems
• Experience working with RTL, physical design, and CAD tool flows; contribute outside core DV responsibilities as needed.

• Post graduate degree in Electrical or Computer Engineering, Computer Science, or in a STEM related field
• Experience with formal verification tools (JasperGold, VC Formal, or similar) and emulation or FPGA-based verification; track record of combining formal and simulation for unified bug closure
• Prior work with system IPs such as MMUs (SMMU or IOMMU) and interrupt controllers, and working knowledge of the associated software stacks

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