Senior Memory Subsystem Architect

NVIDIA has continuously reinvented itself. Our invention of the GPU sparked the growth of the PC gaming market, redefined modern computer graphics, and revolutionized parallel computing. Today, research in artificial intelligence is booming worldwide, which calls for highly scalable and massively parallel computation horsepower that NVIDIA GPUs excel. NVIDIA is a “learning machine” that constantly evolves by adapting to new opportunities that are hard to solve, that only we can address, and that matter to the world. This is our life’s work , to amplify human creativity and intelligence. As an NVIDIAN, you’ll be immersed in a diverse, supportive environment where everyone is inspired to do their best work. Come join our diverse team and see how you can make a lasting impact on the world!

NVIDIA is seeking a motivated memory subsystem architects to work with a team to solve complex problems while optimizing performance, area, complexity, and power on leading-edge SoC systems . This team helps build new and innovative products tailored to NVIDIA’s world changing solutions for Data center, Autonomous vehicles, deep-learning, and gaming.

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  Developing architecture and micro-architecture to improve the state-of-the-art in memory system optimizing along the axes of performance, power efficiency, complexity, area, effort, and schedule.

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  Performance modeling and simulation of features to improve memory system efficiency.

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  Implementing and maintaining high-level performance and functional models.

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  Analyzing benchmarks, application workloads, and performance simulation results to identify tradeoffs in areas of micro-architectural optimizations.

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  Debugging performance and functional issues with high-level models, RTL simulation, and silicon.

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  Working with various cross functional teams like ASIC design and verification, software, product development team, marketing in developing the comprehensive solution.

• Master degree or equivalent experience in Electrical Engineering, Computer Science, Computer Engineering or related field (or the equivalent experience).

• 4+ years of meaningful work experience in SoC Architecture and development specifically in one or more domains of MMU and address translation, memory caching, interconnects, and DRAM controllers.

• Strong communication and interpersonal skills are required along with the ability to work in a dynamic, product oriented, distributed team.

• Significant understanding of Performance (Bandwidth and Latency), Quality of Service and its impact on the overall system performance

• Practical experience in developing and using Performance model for early Architecture analysis

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