USD 150000-320000/yr

HBM Logic Architect

United StatesUnited States·San Josemid
ArchitectConstruction & Real Estate
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Quick Summary

Key Responsibilities

Define, design, and validate digital IP for ASIC/SoC products. Perform RTL design and implementation based on approved specifications.

Technical Tools
ArchitectConstruction & Real Estate

This role involves establishing close technical engagement with key US-based customers to address immediate base-die architectural challenges in HBM and 3D-stacked DRAM. You will be responsible for building a compact and focused HBM Architect Design team in the US to directly support these critical customer interactions. The position also requires developing advanced and customized HBM architectures for future products while strengthening competitiveness through sustained collaboration and technical leadership.

Responsibilities

~1 min read
  • Define, design, and validate digital IP for ASIC/SoC products.
  • Perform RTL design and implementation based on approved specifications.
  • Collaborate with cross-functional teams to define IP functionality, behavior, and architecture.
  • Review digital IP requirements and evaluate architecture options based on PPA targets.
  • Determine or contribute to architecture decisions for digital IP implementation.
  • Develop and verify RTL designs using industry-standard design methodologies.
  • Provide design guidance and support for physical design implementation.
  • Strengthen digital IP design capabilities for HBM and next-generation DRAM development by securing personnel for real-time support near customer sites.
  • Drive system-level co-optimization beyond standalone DRAM design.
  • Build deep technical partnerships with U.S.-based customers.
  • Improve competitiveness through close engagement with customers in the U.S.

Requirements

~1 min read
  • Bachelor’s degree or higher in Electrical Engineering or a related discipline(Master’s preferred).
  • 5+ years of relevant experience in semiconductor, ASIC/SoC, digital IP, memory, or PHY design.
  • High-speed digital PHY or high-speed IP design and analysis
  • DRAM memory controller design and analysis
  • DRAM DFT/DFD architecture, design, or analysis
  • PHY/TSV bit macro design, TSV PHY hard macro design, or 3D PHY design
  • Experience in PPA (Power, Performance, Area) optimization, preferred.

What We Offer

~1 min read
Top Tier health insurance at no employee cost
Paid day offs: PTO + Company Holidays + Happy Fridays
Paid Parental Leave Program
401k Matching
Educational reimbursement up to $10,000 per year for job-related higher education degree
Donation Matching and volunteering opportunities
Corporate discount programs
Free Breakfast/Lunch/Dinner provided to employees

SKHYA is an Equal Employment Opportunity Employer. We provide equal employment opportunities to all qualified applicants and employees and prohibit discrimination and harassment of any type without regard to race, sex, pregnancy, sexual orientation, religion, age, gender identity, national origin, color, protected veteran or disability status, genetic information or any other status protected under federal, state, or local applicable laws. 

Location & Eligibility

Where is the job
San Jose, United States
On-site at the office
Who can apply
US

Listing Details

Posted
July 28, 2026
First seen
July 29, 2026
Last seen
July 29, 2026

Posting Health

Days active
0
Repost count
0
Trust Level
79%
Scored at
July 29, 2026

Signal breakdown

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HBM Logic ArchitectUSD 150000-320000