Senior Principal Engineer - Verification

1. Defines the verification architecture for complex SoCs, such as multi-cluster CPUs, coherent interconnects, PCIe, CXL and DDR/HBM subsystems, and chiplet or UCIe-based designs.

2. Owns organization-level verification methodology: UVM framework standards, coding guidelines, VIP strategy, regression and coverage infrastructure.

3. Expert in advanced techniques: formal verification, emulation and hybrid emulation, Portable Stimulus (PSS), and hardware/software co-verification.

4. Evaluates and selects EDA tools, VIPs and flows, and builds strong relationships with EDA vendors.

5. Is the escalation point for the hardest bugs, sign-off disputes and verification-closure risks across projects.

6. Provides technical solutioning for pre-sales: verification approach, effort models and risk assessment for customer proposals.

7. Drives AI/ML-assisted verification initiatives, such as coverage closure, regression triage and test generation.

8. Mentors principals and technical leads, and builds technical depth across the verification practice.

9. Represents the company in technical discussions with customer architects.

Must-have skills

verification architecture, SoC verification, UVM framework

Good-to-have skills

EDA tool evaluation, AI/ML verification initiatives, chiplet or UCIe experience.