Digital Design Engineer Jobs

Responsibilities MaxLinear is seeking a Senior Principal Digital Design Engineer to join our team. In this role, you will focus on the following: Define microarchitecture for complex subsystems (e.g., 200/400G 802.3, PCIe 6/7, DSP, FEC, data compression, AI/HW accelerators) Analyze standards (PCI-SI

About MBRYONICS MBRYONICS is at the forefront of free space optical communications. Our product portfolio covers a wide range of emerging technologies from photonic integrated circuits to advanced optical systems and embedded software solutions. Our optical communications systems are integrated and

Design and support digital hardware platforms for semiconductor packaging machines. Design and develop digital circuits using FPGAs and microcontrollers. Develop digital interfaces for machine subsystems and system integration. Perform hardware verification, debugging, and troubleshooting. Degree or

About MBRYONICS MBRYONICS is at the forefront of free space optical communications. Our product portfolio covers a wide range of emerging technologies from photonic integrated circuits to advanced optical systems and embedded software solutions. Our optical communications systems are integrated and

Who We Are HP IQ is HP’s new AI innovation lab. Combining startup agility with HP’s global scale, we’re building intelligent technologies that redefine how the world works, creates, and collaborates. We’re assembling a diverse, world-class team—engineers, designers, researchers, and product minds—fo

Join the leading chiplet startup! As an Eliyan Staff Digital Design Engineer, you will be working at a fast-paced early-stage startup creating technologies that fuel tomorrow's chiplet-based systems with best-in-class power, area, manufacturability, and design flexibility. In this role you will lead

Join the leading chiplet startup! As an Eliyan digital designer, you will be working at a fast-paced early-stage startup creating technologies that fuel tomorrow’s chiplet based systems with best-in-class power, area, manufacturability, and design flexibility. You will be developing micro-architectu

Key Responsibilities: Design and implement sensor timing control logic and contribute to ISP system-level integration Participate in chip-level architecture definition, including analog interfaces, control logic, image data processing pipelines, and power/performance/area (PPA) trade-offs Integrate

Omni Design is working on exciting solutions and chips for next generation automotive and space applications and looking for talented and capable engineers. The Senior Design Engineer will be responsible for the RTL and FPGA design and verification of the various modules for the next generation digi

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integr

Job Description: Design cost effective controller with high performance, low power and small area for cellular modem. This position will work with multi-nation teams in leading-edge process node and be involved in: - Perform CPU development and design integration for CPU subsystem. - Micro-architect

Job Description:Design cost effective controller with high performance, low power and small area for cellular modem. This position will work with multi-nation teams in leading-edge process node and be involved in: - Perform CPU development and design integration for MIPS CPU subsystem. - Explore lat

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integr

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integr

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integr

Key Responsibilities: Design and implement sensor timing control logic and contribute to ISP system-level integration Participate in chip-level architecture definition, including analog interfaces, control logic, image data processing pipelines, and power/performance/area (PPA) trade-offs Integrate

Please Note: To provide the best candidate experience amidst our high application volumes, each candidate is limited to 10 applications across all open jobs within a 6-month period. Advancing the World’s Technology Together Our technology solutions power the tools you use every day--including smartp

A cover letter outlining your motivation to move to Oslo, Norway is required with submittal of your CV. We design and verify: timing and control signals for CMOS pixel array readout & analog/digital converters; image signal processing (ISP) functions such as black level compensation (BLC), defect pi

Responsibilities: As Digital Design Engineer, • Responsible for RTL design and verification using Verilog and System Verilog• Define System Architecture and/or Block level Micro Architecture based on product features and performance requirements, also with gate count and power estimation• Work close

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integr