Senior IP Verification Engineer

• →Responsible for the pre-silicon verification of IP modules or, IP subsystems
• →Responsible for defining and writing IP verification plans based on requirements documents (industry standards, product requirements, IP architecture and IP implementation specifications)
• →Interface to HW, FW, and SW design teams, as well as to architecture and system engineering teams, to understand functionality and application of the IP or subsystem.
• →Responsible for executing verification plan according to the product specification and verification requirements defined by product architects.
• →Responsible for architecting, developing, debugging and running UVM based verification environment for RTL simulation.
• →Define and develop test cases in an appropriate verification framework. Create stimulus and assertions, run simulation, debug test cases on the design models (RTL, power aware RTL, gate level, FPGA, Emulation platform), run regression, collect and analyze code/functional coverage.

• Degree in Electrical Engineering or Computer Science, with 5+ years of experience on IP/Sub-System Verification
• Proven experience in testbench design and development using UVM methodology for IP/Subsystem and SOC.
• Experience in Microcontroller and Microprocessor architecture, Interconnect, Cache Coherency.
• Experience in protocols like AHB/AMBA, Memory (ROM, RAM, Flash, LPDDR/DDR3/4) and memory controllers.
• Advanced knowledge of Verilog, System Verilog, C/C++, Shell.
• Good knowledge in scripting like Perl, TCL or Python is a plus
• High proficiency in Metric Driven Verification concepts, functional and code coverage.
• High proficiency in directed and constrained random methodologies.
• Good knowledge of formal verification methodologies and assertions.
• Experience with debugging of designs pre- and post-silicon, in simulation and on the bench.
• Excellent written and verbal communication skill. 

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