Principal Engineer - IP Verification | nxp

→Self starter with 10-15 years of experience on IP / Sub-system verification on multimillion Gate and complex Design with multiple clocks with minimal supervision
→Testbench and Testplan development to ensure thorough functional verification, and performance aspects of the IP along with Features traceability.
→Experience in microcontroller architecture working with ARM cores, protocols like AHB/AMBA, AXI, Memory (Flash, SRAM,DDR) and memory controllers
→Experience in domains like automotive Graphics / Vision accelerators, Slow and High Speed Serial IP controllers, Networking protocols like Ethernet, would be an added advantage
→Must have experience and strong working knowledge of HVLs like (UVM/SV/C++), HDLs (Verilog/VHDL), PLI/DPI, simulators (NCSim/VCS/ModelSim/Questa).
→Must have experience in end to end IP verification project cycle, including Testbench Strategies, TB development, simulation debugs.
→Good Exposure to formal verification methodology, assertions/SVA, functional coverage, gate level simulations, verification planner and regression management.
→Strong ability to drive verification methodologies is a highly desired for 10+ yrs candidates.
→Exposure to pre silicon validation/emulation is an added advantage.

#LI-2734

Principal Engineer - IP Verification