Sr. Technical Lead - Verification

Desired Skills:

1. Defines the overall verification strategy for a sub-system or SoC, deciding the mix of simulation, formal, emulation and GLS.

2. Architects SoC-level testbenches that combine UVM environments, embedded C tests, interconnect and system-level scenarios.

3. Strong expertise in 2 or more complex protocols, and in reviewing the verification environments built for them.

4. Applies formal verification for connectivity, protocol properties, or unreachability analysis to support coverage.

5. Owns the low-power verification strategy (UPF), including power-aware simulation and checks on power-mode sequences.

6. Owns project schedules, effort estimates, risk tracking and weekly status reports to the customer. 7

. Leads verification plan reviews, bug triage meetings and sign-off reviews with the design and customer teams.

8. Works with design, DFT, firmware and physical design teams to resolve issues across those boundaries. Interviews candidates and grows the technical depth of the team.

9. Exposure to emulation (Palladium, ZeBu, Veloce) or FPGA prototyping is a plus.

SoC or sub-system level verificatio, tape-out

formal veification, emulation, UPF Ownership