Senior Physical Design Engineer

United States·Santa Clarasenior

EngineeringDesign Engineer

1 views0 saves0 applied

Apply Now

Quick Summary

Key Responsibilities

Own RTL to GDS physical implementation flows for synthesis, floor-planning, place and route, clock tree synthesis, timing & power closure, EM/IR,

Requirements Summary

BS, MS in Electrical Engineering or Computer Engineering or related degree Experience in all aspects of physical design including synthesis, floor planning, place & route, timing & power closure,

Technical Tools

EngineeringDesign Engineer

Baya is a fast-moving Series B startup built by serial entrepreneurs with a vision to accelerate intelligent computing in the emerging chiplet era. We focus on software-driven, unified fabric solutions for single-die and multi-die systems. We design and license disruptive intellectual property for use in semiconductor chips, with software development platforms to simplify the design process and reduce the time to market for complex System-on-Chip (SoC) and multi-chiplet systems. This enables our partners to innovate and deliver compelling solutions for data center, infrastructure, AI, Automotive, and Edge IoT markets. We are looking for energetic and dedicated individuals share our passion for enabling innovation and excellence in the semiconductor industry that empowers game-changing products and services!

Job Title: Sr. Physical Design Engineer

Location: Santa Clara, CA

About the role: We are seeking a seasoned Physical Design Engineer with a strong background in all aspects of Physical Design and Implementation flows. The ideal candidate will play a key role in shaping our technology portfolio, bringing expertise and creativity to our solutions

Responsibilities:

Own RTL to GDS physical implementation flows for synthesis, floor-planning, place and route, clock tree synthesis, timing & power closure, EM/IR, PDV and final PD sign off

Own physical design & implementation of high-performance designs from block level to system level components

Deep collaboration with Micro-architects to explore performance, power and area trade-offs for high performance and low power designs

Physical implementation feasibility studies and design recommendations for best PPA

Develop methodologies and recipes for various stages of physical implementation

Perform various physical design validation (PDV) flows for Timing, Power, EM/IR, etc. to ensure physical design quality

Perform design rule checking (DRC), (LVS) checks, and other physical verification tasks

Qualifications:

BS, MS in Electrical Engineering or Computer Engineering or related degree

Experience in all aspects of physical design including synthesis, floor planning, place & route, timing & power closure, EM/IR, physical design validation, etc

Experience with synthesis, place & route, static timing analysis and PDV tools

Experience in implementing clock trees and power grids

Experience with scripting for physical design flow automation

Experience with Synopsys Design Compiler, Prime Time, ICC, Fusion Compiler etc.

Good knowledge of high-performance and low-power microarchitecture and logic design principles

Understanding of modern (sub 7nm) sub-micron technology nodes and device physics

Basic knowledge of System/SoC Architecture and System Verilog RTL coding

Strong communication and collaboration skills