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Principal RFIC-PLL Design Engineer

PolandPoland·Krakówlead
EngineeringDesign Engineer
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Quick Summary

Key Responsibilities

• Lead the design, development and integration of PLLs in advanced CMOS and SiGe technologies, focusing on performance optimization and trade-off analysis.

Technical Tools
EngineeringDesign Engineer

Application close date:

Applications will be accepted on an ongoing basis until the requisition is closed.

At Blue Origin, we envision millions of people living and working in space for the benefit of Earth. We’re working to develop reusable, safe, and low-cost space vehicles and systems within a culture of safety, collaboration, and inclusion. Join our team of problem solvers as we add new chapters to the history of spaceflight!  

Blue Origin is pioneering the future of space-based connectivity with TeraWave, a revolutionary satellite communications network designed to deliver symmetrical data speeds of up to 6 Tbps anywhere on Earth. This network will service tens of thousands of enterprise, data center, and government users who require reliable connectivity for critical operations.

We are seeking a Principal PLL Design Engineer to lead the development of Phase-Locked Loops (PLLs) in advanced CMOS/SiGe processes. This role requires extensive design experience, particularly at mmWave frequencies, and is essential for advancing our technology offerings in space communication systems. You will be responsible for delivering state-of-the-art performance while contributing to innovative solutions that drive Blue Origin's mission of enabling millions to live and work in space for the benefit of Earth.


Key Responsibilities: 


• Lead the design, development and integration of PLLs in advanced CMOS and SiGe technologies, focusing on performance optimization and trade-off analysis.

• Utilize full proficiency in Spectre and AMS flows to develop high-performance PLL circuits.

• Collaborate with RF system architects to define requirements for PLLs and their sub-blocks based on system specifications, ensuring seamless integration into RF payloads and terminals.

• Oversee layout, top-level integration, floorplanning, and verification of the overall design for successful tape-out cycle.

• Work closely with validation and product engineers to develop test plans, facilitate bring-up, optimize performance, and ensure reliable & high-yield production cycles.

• Investigate and implement fundamental analog building blocks to enhance overall circuit performance and mentor junior engineers for best design practices in analog domain.


Basic Qualifications:


• MS or PhD in Electrical Engineering or a related technical discipline.

• 10+ years of experience in the design and development of high-speed (>20GHz) PLLs and LOGEN for high-performance applications at RF and mmWave frequencies.

• Full proficiency in mixed-mode and RF modeling, simulation, and verification methodologies using toolsets such as MATLAB, Spectre, SystemVerilog, and AMS.

• Extensive experience in PLL silicon characterization and debugging.
• Strong background in fundamental analog/RF building blocks, including amplifiers, filters, and mixers.


Preferred Skills:


• Strong expertise in loop design for phase noise/jitter, spur profile, area, and power optimization.

• Extensive experience with fundamental analog building blocks such as LDOs, bias generators, and operational amplifiers.

• Fundamental understanding of device physics for process selection and performance optimization.

• Familiarity with digital design, digital verification, and SystemVerilog modeling.

Don’t meet all desired requirements? Studies have shown that some people are less likely to apply to jobs unless they meet every single desired qualification. At Blue Origin, we are dedicated to building an authentic workplace, so if you’re excited about this role but your past experience doesn’t align perfectly with every desired qualification in the job description, we encourage you to apply anyway. You may be just the right candidate for this or other roles.


Candidates may be subject to verification and BGS screening as per applicable law.


Location & Eligibility

Where is the job
Kraków, Poland
On-site at the office
Who can apply
PL

Listing Details

Posted
October 13, 2026
First seen
October 13, 2026
Last seen
October 13, 2026

Posting Health

Days active
0
Repost count
0
Trust Level
56%
Scored at
October 14, 2026

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Principal RFIC-PLL Design Engineer